PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 136

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
EN_ICV ... Enable Illegal Code Violation
0: normal operation
1: ICV enabled. The receipt of at least one illegal code violation within one multiframe is
L1SW ... Enable Layer 1 State Machine in Software
0: Layer 1 state machine of the SBCX-X is used
1: Layer 1 state machine is disabled. The functionality can be realized in software.
For general information please refer to
EXLP ... External loop
In case the analog loopback is activated with C/I = ARL or with the LP_A bit in the
TR_CMD register the loop is a
0: internal loop next to the line pins
1: external loop which has to be closed between SR1/2 and SX1/SX2
Note:The external loop is only useful if bit DIS_TX of register TR_CONF2 is set to ’0’.
For general information please refer to
LDD ... Level Detection Discard
0: Automatic clock generation after detection of any signal on the line in
1: No clock generation after detection of any signal on the line in power down state
Note: If an interrupt by the level detect circuitry is generated, the microcontroller has to
For general information please refer to
Data Sheet
indicated by the C/I indication ’1011’ (CVR) in two consecutive IOM frames.
The commands can be written to register TR_CMD and the status can be read from
TR_STA.
power down state
set this bit to ’0’ for an activation of the S/T interface.
Chapter
Chapter
Chapter 3.3.8
136
3.5.
3.3.10.
and
Detailed Register Description
Chapter
3.7.6.
PEB 3081
PEF 3081
2000-09-27