PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 154

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
4.3.5
Value after reset: 00
TRC_CR
Write access to this register is possible if IOM_CR.CI_CS = 0 or IOM_CR.CI_CS = 1.
Read access to this register is possible only if IOM_CR.CI_CS = 1.
CS2-0 ... Channel Select for the Transceiver C/I0 Channel
This register is used to select one of eight IOM channels to which the transceiver C/I0
channel data is related to. The reset value is determined by the channel select pins CH2-
0 and the MODE2-bit.
4.3.6
Value after reset: 80
DCI_CR
Read and write access to this register is only possible if IOM_CR.CI_CS = 0. It should
be noted that a writing the DCI_CR register will also perform a write access to DCIC_CR,
i.e. the lower 3 bits of DCI_CR will be written to DCIC_CR.CS2-0.
DPS_CI1 ... Data Port Selection CI1 Handler Data
0: The CI1 handler data is output on DD and input from DU
1: The CI1 handler data is output on DU and input from DD
EN_CI1 ... Enable CI1 Handler Data
0: CI1 handler data access is disabled
1: CI1 handler data access is enabled
Note: The timeslot for the C/I1 handler cannot be programmed but is fixed to IOM
Data Sheet
channel 1.
7
TRC_CR - Control Register Transceiver C/I0 (IOM_CR.CI_CS=1)
7
DCI_CR - Control Register for CI1 Handler (IOM_CR.CI_CS=0)
DPS_
CI1
0
EN_
H
H
CI1
0
0
0
0
0
154
0
0
0
Detailed Register Description
CS2-0
0
0
0
0
RD/WR (50)
RD/WR (53)
PEB 3081
PEF 3081
2000-09-27