PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 168

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
4.4.4
Value after reset: FF
AUXM
For the MASK register following logical states are applied:
0: Interrupt is enabled
1: Interrupt is disabled
Each interrupt source in the AUXI register can selectively be masked/disabled by setting
the corresponding bit in AUXM to ’1’. Masked interrupt status bits are not indicated when
AUXI is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ’0’.
4.4.5
Value after reset: 00
MODE1
WTC1, 2 ... Watchdog Timer Control 1, 2
After the watchdog timer mode has been selected (RSS = ’11’) the watchdog timer is
started. During every time period of 128 ms the microcontroller has to program the
WTC1 and WTC2 bit in the following sequence
to reset and restart the watchdog timer.
If WTC1/2 is not written fast enough in this way, the timer expires and a WOV-interrupt
(AUXI register) together with a reset pulse is generated.
Data Sheet
7
7
AUXM - Auxiliary Mask Register
MODE1 - Mode1 Register
1
0
1.
2.
H
H
1
0
WTC1
1
0
EAW
0
WTC1 WTC2
WOV
WTC2
0
1
168
TIN
CFS
1
Detailed Register Description
RSS2 RSS1
1
0
0
1
RD/WR (62)
PEB 3081
PEF 3081
2000-09-27
WR (61)