PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 152

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
4.3.3
CDAx_
CR
Register
CDA1_CR
CDA2_CR
For general information please refer to
EN_TBM ... Enable TIC Bus Monitoring
0: The TIC bus monitoring is disabled
1: The TIC bus monitoring with the CDAx0 register is enabled. The TSDPx0 register
(This selection is only valid if IOM_CR.TIC_DIS = 0).
EN_I1, EN_I0 ... Enable Input CDAx0, CDAx1
0: The input of the CDAx0, CDAx1 register is disabled
1: The input of the CDAx0, CDAx1 register is enabled
EN_O1, EN_O0 ... Enable Output CDAx0, CDAx1
0: The output of the CDAx0, CDAx1 register is disabled
1: The output of the CDAx0, CDAx1 register is enabled
SWAP ... Swap Inputs
0: The time slot and data port for the input of the CDAxy register is defined by its own
1: The input (time slot and data port) of the CDAx0 is defined by the TSDP register of
Data Sheet
must be set to 08
TSDPxy register. The data port for the CDAxy input is vice versa to the output setting
for CDAxy.
CDAx1 and the input of CDAx1 is defined by the TSDP register of CDAx0. The data
port for the CDAx0 input is vice versa to the output setting for CDAx1. The data port
for the CDAx1 input is vice versa to the output setting for CDAx0. The input definition
for time slot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 to
CDAx0. The outputs are not affected by the SWAP bit.
7
CDAx_CR - Control Register Controller Data Access CH1x
0
Register Address
4E
4F
H
for monitoring from DU or 88
H
H
0
TBM
EN_
EN_I1 EN_I0 EN_O1 EN_O0 SWAP
Chapter
Value after Reset
00
00
H
H
152
3.7.1.1.
H
for monitoring from DD, respectively.
Detailed Register Description
0
PEB 3081
PEF 3081
2000-09-27
RD/WR
(4E-4F)