PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 145

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
4.1.18
Value after reset: FF
MASKTR
The transceiver interrupts LD, RIC, SQC and SQW are enabled (0) or disabled (1).
4.1.19
Value after reset: 000000xx
TR_
MODE
For general information please refer also to
DCH_INH ... D-Channel Inhibit (NT, LT-S, Int. NT mode only)
Setting this bit to ’1’ has the effect that the S-transceiver blocks the access to the D-
channel on S by inverting the E-bits.
The pin DCI, which performs the same funtion, is internally combined (EXOR-logic) with
DCH_INH, i.e. either setting the bit to ’1’ or pulling the pin high will block the D-channel
access, however activating pin and bit simultaneously must not be done.
If this bit was not set before, reading DCH_INH reflects the status on pin DCI, i.e. the D-
channel inhibit function is controlled by the pin. If the function should be controlled by
programming DCH_INH, the pin DCI must be strapped to “0” or “1”.
Data Sheet
7
7
MASKTR - Mask Transceiver Interrupt
TR_MODE - Transceiver Mode Register 1
1
0
H
1
0
B
1
0
1
0
145
DCH_
INH
Chapter
LD
MODE
RIC
2
3.7.5.4.
Detailed Register Description
MODE
SQC
1
0
0
MODE
SQW
0
RD/WR (3A)
RD/WR (39)
PEB 3081
PEF 3081
2000-09-27