PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 200

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

AOE
Note: An interrupt is only generated if the corresponding mask bit in AUXM is reset.
For general information please refer to
4.3.3
Value after reset: FF
For general information please refer to
OE7-0 ... Output Enable for AUX7 - AUX0
0: Pin AUX7-0 is configured as output. The value of the corresponding bit in the ATX
register is driven on AUX7-0.
1: Pin AUX7-0 is configured as input. The value of the corresponding bit can be read from
the ARX register.
Note: In NT and LT modes the pins AUX0-2 are not available as I/O pins.
Data Sheet
This configuration is only valid if the corresponding output enable bit in AOE is
disabled.
If pins AUX7, AUX6 are to be used as interrupt input, OE7, OE6 must be set to 1.
If pins AUX7, AUX5 and AUX4 are not used as I/O pins (see ACFG2), the
corresponding OEx bit cannot be set, but delivers the mode dependent direction
(input/output) in that function upon a read access. If the secondary function is
disabled, the direction of the pin as I/O pin is valid again.
7
AOE - Auxiliary Output Enable Register
OE7
OE6
H
OE5
OE4
Chapter
Chapter
200
OE3
3.8.1.
3.8.1.
OE2
Detailed Register Description
OE1
0
OE0
PSB/PSF 21150
RD/WR (3E)
2003-01-30
IPAC-X