PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 207

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

DCI_CR
The registers BCHA_TSDP_BC1/2 and BCHB_TSDP_BC1/2 (see above) select the
IOM-2 timeslots for B-channel controller access. For each of the B-channel controllers
(BCHA, BCHB) two 8-bit timeslots can be selected (position and direction).
This register BCHx_CR is used to select the position (CS2-0) and direction (DPS_D) of
the 2-bit timeslot for each of the two B-channel controllers, and each of the three selected
timeslots (2 x 8-bit and 2-bit) is individually enabled/disabled (EN_BC1, EN_BC2,
EN_D).
DPS_D ... Data Port Selection for D-Channel Timeslot access
0: The B-channel controller data is output on DD.
1: The B-channel controller data is output on DU.
EN_D ... Enable D-Channel Timeslot (2-bit) for B-Channel controller access
EN_BC2 ... Enable B2-Channel Timeslot (8-bit) for B-Channel controller access
EN_BC1 ... Enable B1-Channel Timeslot (8-bit) for B-Channel controller access
These bits individually enable/disable the B-channel access to the 2-bit and the two 8-
bit timeslots.
0: B-channel B/A does not access timeslot data B1, B2 or D, respectively.
1: B-channel B/A does access timeslot data B1, B2 or D, respectively.
Note: The terms B1/B2 should not imply that the 8-bit timeslots must be located in the
CS2-0 ... Channel Select for D-Channel Timeslot access
This register is used to select one of eight IOM channels. If enabled (EN_D=1), the B-
channel controller is connected to the 2-bit D-channel timeslot of that IOM channel.
Note: The reset value is determined by the channel select pins CH2-0 which are directly
4.4.7
Value after reset: A0
Data Sheet
The B-channel controller data is input from DU.
The B-channel controller data is input from DD.
first/second IOM-2 timeslots, it’s simply a placeholder for the 8-bit timeslot position
selected in the registers BCHA_TSDP_BC1/2 and BCHB_TSDP_BC1/2.
mapped to CS2-0.
7
DCI_CR - Control Register for D and CI1 Handler
(IOM_CR.CI_CS=0)
DPS_
CI1
EN_
CI1
H
EN_D
D_
EN_B2
D_
207
EN_B1
D_
Detailed Register Description
CS2-0
0
PSB/PSF 21150
RD/WR (53)
2003-01-30
IPAC-X