PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 31

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Table 2
Pin No.
MQFP-64
TQFP-64
58
59
27
6
4
2, 42
Power Supply
8, 18, 33,
56
46
Data Sheet
Symbol Input (I)
MODE1
EAW
ACL
C768
RSTO
TP
n.c.
V
V
DD
DDA
IPAC-X Pin Definitions and Functions (cont’d)
Output (O)
Open Drain
(OD)
I
I
O
O
OD
I
I
–
–
Function
The pin function depends on the setting of MODE0.
If MODE0=1: Mode 1 Select
A LOW selects LT-T mode and a HIGH selects LT-
S mode.
If MODE0=0: External Awake
If a falling edge on this input is detected, the IPAC-
X generates an interrupt and, if enabled, a reset
pulse.
Activation LED
This pin can either function as a programmable
output or it can automatically indicate the activated
state of the S interface by a logic ’0’.
An LED with pre-resistance may directly be
connected to ACL.
Clock Output
A 7.68 MHz clock is output to support other devices.
This clock is not synchronous to the S interface.
Reset Output
Low active reset output, either from a watchdog
timeout or programmed by the host.
Test Pin
Must be connected to
not connected
Digital Power Supply Voltage
(3.3 V ± 5 %)
Analog Power Supply Voltage
(3.3 V ± 5 %)
31
V
SS
.
Pin Configuration
PSB/PSF 21150
2003-01-30
IPAC-X