PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 167
PEB3086HV14XP
Manufacturer Part Number
PEB3086HV14XP
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEB3086HV14XP.pdf
(262 pages)
Specifications of PEB3086HV14XP
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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STARD
CMDRD
4.1.5
Value after reset: 40
XDOV ... Transmit Data Overflow
More than 16 or 32 bytes (according to selected block size) have been written to the
XFIFOD, i.e. data has been overwritten.
XFW ... Transmit FIFO Write Enable
Data can be written to the XFIFOD. This bit may be polled instead of (or in addition to)
using the XPR interrupt.
RACI ... Receiver Active Indication
The D-channel HDLC receiver is active when RACI = ’1’. This bit may be polled. The
RACI bit is set active after a begin flag has been received and is reset after receiving an
abort sequence.
XACI ... Transmitter Active Indication
The D-channel HDLC-transmitter is active when XACI = ’1’. This bit may be polled. The
XACI-bit is active when an XTF-command is issued and the frame has not been
completely transmitted
4.1.6
Value after reset: 00
RMC ... Receive Message Complete
Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By
setting this bit, the microcontroller confirms that it has fetched the data, and indicates that
the corresponding space in the RFIFOD may be released.
Data Sheet
7
7
XDOV XFW
STARD - Status Register D-Channel
CMDRD - Command Register D-Channel
RMC RRES
H
H
0
0
STI
0
167
RACI
XTF
0
0
Detailed Register Description
XACI
XME XRES
0
0
0
PEB 3086
2003-01-30
ISAC-SX
WR (21)
RD (21)
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