M471B5773DH0-YK0 Samsung Semiconductor, M471B5773DH0-YK0 Datasheet - Page 13

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M471B5773DH0-YK0

Manufacturer Part Number
M471B5773DH0-YK0
Description
Manufacturer
Samsung Semiconductor
Datasheet

Specifications of M471B5773DH0-YK0

Lead Free Status / Rohs Status
Supplier Unconfirmed
Unbuffered SODIMM
10.2 V
The dc-tolerance limits and ac-noise limits for the reference voltages V
V
thermore V
which setup and hold is measured. System timing and voltage budgets need to account for V
data-eye of the input signals.
Timing and voltage effects due to ac-noise on V
The voltage levels for setup and hold time measurements V
"V
This clarifies, that dc-variations of V
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V
V
REF
REF
REF
(t) as a function of time. (V
(DC) is the linear average of V
" shall be understood as V
REF
REF
Tolerances
(t) may temporarily deviate from V
voltage
REF
REF
stands for V
(DC), as defined in Figure 1.
REF
REF
(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of V
affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
REF
REFCA
REF
up to the specified limit (+/-1% of V
(DC) by no more than ± 1% V
and V
datasheet
IH
REFDQ
(AC), V
likewise).
IH
(DC), V
REFCA
- 14 -
IL
and V
(AC) and V
DD
.
REFDQ
DD
) are included in DRAM timings and their associated deratings.
IL
are illustrate in Figure 1. It shows a valid reference voltage
(DC) are dependent on V
REF
(DC) deviations from the optimum position within the
V
V
SS
DD
REF
time
DDR3L SDRAM
.
REF
ac-noise.
Rev. 1.0
REF
. Fur-

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