M471B5773DH0-YK0 Samsung Semiconductor, M471B5773DH0-YK0 Datasheet - Page 24

• Manufacturer Part Number: M471B5773DH0-YK0
• Manufacturer: Samsung Semiconductor

Specifications of M471B5773DH0-YK0

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Unbuffered SODIMM
14. Input/Output Capacitance
[ Table 15 ] Input/Output Capacitance
NOTE : This parameter is Component Input/Output Capacitance so that is different from Module level Capacitance.
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance
(CK and CK)
Input capacitance delta
(CK and CK)
Input capacitance
(All other input-only pins)
Input/Output capacitance delta
(DQS and DQS)
Input capacitance delta
(All control input-only pins)
Input capacitance delta
(all ADD and CMD input-only pins)
Input/output capacitance delta
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input/output capacitance of ZQ pin
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance
(CK and CK)
Input capacitance delta
(CK and CK)
Input capacitance
(All other input-only pins)
Input capacitance delta
(DQS and DQS)
Input capacitance delta
(All control input-only pins)
Input capacitance delta
(all ADD and CMD input-only pins)
Input/output capacitance delta
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input/output capacitance of ZQ pin
The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with
V
termination off.
DD
, V
DDQ
, V
Parameter
SS
, V
SSQ
applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). V
CDI_ADD_CMD
CDI_ADD_CMD
CDI_CTRL
CDI_CTRL
Symbol
CDDQS
CDDQS
CDCK
CDCK
CDIO
CDIO
CZQ
CCK
CZQ
CCK
CIO
CIO
CI
CI
datasheet
0.75
0.75
Min
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
1.5
0.8
1.5
0.8
DDR3-800
0
0
0
0
-
-
Max
0.15
0.15
2.5
1.6
1.3
0.2
0.3
0.5
0.3
3.0
1.6
1.5
0.2
0.3
0.5
0.3
3
3
1.35V
1.5V
- 25 -
0.75
0.75
Min
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
1.5
0.8
1.5
0.8
DDR3-1066
0
0
0
0
-
-
Max
0.15
0.15
2.5
1.6
1.3
0.2
0.3
0.5
0.3
2.7
1.6
1.5
0.2
0.3
0.5
0.3
3
3
TBD
TBD
0.75
TBD
TBD
TBD
TBD
TBD
0.75
Min
-0.4
-0.4
-0.5
1.5
1.5
0.8
DDR3-1333
0
0
-
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.15
0.15
2.3
1.3
2.5
1.4
1.3
0.2
0.4
0.3
3
DD
=V
DDQ
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.75
0.75
Min
-0.4
-0.4
-0.5
1.2
1.4
0.8
DDR3-1600
0
0
-
=1.5V, V
DDR3L SDRAM
BIAS
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max
0.15
0.15
2.3
1.3
2.3
1.4
1.3
0.2
0.4
0.3
3
=V
DD
Units
/2 and on-die
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Rev. 1.0
2,3,9,10
2,3,9,10
2, 3, 12
2, 3, 12
2,3,7,8
2,3,7,8
NOTE
2,3,11
2,3,11
2,3,5
1,2,3
2,3,4
2,3,6
2,3,5
1,2,3
2,3,4
2,3,6
2,3
2,3