M471B5773DH0-YK0 Samsung Semiconductor, M471B5773DH0-YK0 Datasheet - Page 17

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M471B5773DH0-YK0

Manufacturer Part Number
M471B5773DH0-YK0
Description
Manufacturer
Samsung Semiconductor
Datasheet

Specifications of M471B5773DH0-YK0

Lead Free Status / Rohs Status
Supplier Unconfirmed
Unbuffered SODIMM
10.3.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage V
cross point of true and complement signal to the mid level between of V
[ Table 6 ] Cross point voltage for differential input signals (CK, DQS) : 1.35V
NOTE :
1. The relationbetween Vix Min/Max and VSEL/VSEH should satisfy following.
[ Table 7 ] Cross point voltage for differential input signals (CK, DQS) : 1.5V
NOTE :
1. Extended range for V
(VDD/2) + Vix(Min) - VSEL ≥ 25mV
VSEH - ((VDD/2) + Vix(Max)) ≥ 25mV
Symbol
Symbol
±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.
V
V
V
V
IX
IX
IX
IX
Differential Input Cross Point Voltage relative to V
Differential Input Cross Point Voltage relative to V
Differential Input Cross Point Voltage relative to V
Differential Input Cross Point Voltage relative to V
IX
is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing V
Parameter
Parameter
V
IX
datasheet
DD
DD
DD
DD
/2 for CK,CK
/2 for DQS,DQS
/2 for CK,CK
/2 for DQS,DQS
Figure 4. V
V
DD
IX
and V
- 18 -
IX
Definition
SS
.
V
IX
DDR3L-800/1066/1333/1600
-150
-150
-150
-175
-150
Min
Min
DDR3-800/1066/1333/1600
V
CK, DQS
V
CK, DQS
V
DD
DD
SS
/2
Max
Max
150
150
150
175
150
DDR3L SDRAM
IX
is measured from the actual
SEL
/ V
SEH
Unit
Unit
mV
mV
mV
mV
mV
of at least V
Rev. 1.0
NOTE
NOTE
1
1
DD
/2

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