M471B5773DH0-YK0 Samsung Semiconductor, M471B5773DH0-YK0 Datasheet - Page 30

• Manufacturer Part Number: M471B5773DH0-YK0
• Manufacturer: Samsung Semiconductor

Specifications of M471B5773DH0-YK0

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Unbuffered SODIMM
16. Timing Parameters by Speed Grade
[ Table 20 ] Timing Parameters by Speed Bin
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
Clock Period
Average high pulse width
Average low pulse width
Clock Period Jitter
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
Cumulative error across n = 13, 14 ... 49, 50 cycles
Absolute clock HIGH pulse width
Absolute clock Low pulse width
Data Timing
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
Data setup time to DQS, DQS referenced to
V
Data hold time from DQS, DQS referenced to
V
Data setup time to DQS, DQS referenced to
V
DQ and DM Input pulse width for each input
IH
IH
IH
(AC)V
(AC)V
(AC)V
IL
IL
IL
(AC) levels
(AC) levels
(AC) levels
Parameter
Speed
tCK(DLL_OF
tERR(10per)
tERR(11per)
tERR(12per)
tJIT(per, lck)
tJIT(cc, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(nper)
tDH(base)
tDH(base)
tDS(base)
tDS(base)
tDS(base)
tDS(base)
tCK(avg)
tCK(abs)
tCH(avg)
tCH(abs)
tCL(avg)
tJIT(per)
tCL(abs)
tHZ(DQ)
Symbol
tLZ(DQ)
tJIT(cc)
tDQSQ
DC100
AC160
AC175
AC135
AC150
tDIPW
DC90
tQH
F)
tCK(avg)min +
tJIT(per)min
- 147
- 175
- 194
- 209
- 222
- 232
- 241
- 249
- 257
- 263
- 269
-100
-800
MIN
0.47
0.47
0.43
0.43
0.38
160
150
140
125
600
-90
90
75
datasheet
8
-
-
DDR3-800
200
180
tCK(avg)max +
tJIT(per)max
MAX
0.53
0.53
100
147
175
194
209
222
232
241
249
257
263
269
200
400
400
90
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)min +
tJIT(per)min
- 31 -
- 132
- 157
- 175
- 188
- 200
- 209
- 217
- 224
- 231
- 237
- 242
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
0.47
0.47
0.43
0.43
0.38
-600
MIN
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
110
100
490
-90
-80
40
25
90
75
8
-
-
DDR3-1066
180
160
tCK(avg)max +
tJIT(per)max
See Speed Bins Table
MAX
0.53
0.53
132
157
175
188
200
209
217
224
231
237
242
150
300
300
90
80
-
-
-
-
-
-
-
-
-
-
-
1.35V
1.35V
1.35V
tCK(avg)min +
1.5V
1.5V
1.5V
tJIT(per)min
- 118
- 140
- 155
- 168
- 177
- 186
- 193
- 200
- 205
- 210
- 215
0.47
0.47
0.43
0.43
0.38
-500
MIN
400
-80
-70
75
65
45
30
8
-
-
-
-
DDR3-1333
160
140
tCK(avg)max +
tJIT(per)max
MAX
0.53
0.53
118
140
155
168
177
186
193
200
205
210
215
125
250
250
80
70
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)min +
tJIT(per)min
0.47
0.47
-103
-122
-136
-147
-155
-163
-169
-175
-180
-184
-188
0.43
0.43
0.38
-450
MIN
360
-70
-60
55
45
25
10
DDR3L SDRAM
8
-
-
-
-
DDR3-1600
140
120
tCK(avg)max +
tJIT(per)max
MAX
0.53
0.53
103
122
136
147
155
163
169
175
180
184
188
100
225
225
70
60
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Units
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Rev. 1.0
13,14, f
13,14, f
NOTE
13, g
d, 17
d, 17
d, 17
d, 17
24
25
26
13
28
6