M471B5773DH0-YK0 Samsung Semiconductor, M471B5773DH0-YK0 Datasheet - Page 31

• Manufacturer Part Number: M471B5773DH0-YK0
• Manufacturer: Samsung Semiconductor

Specifications of M471B5773DH0-YK0

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Unbuffered SODIMM
[ Table 20 ] Timing Parameters by Speed Bin (Cont.)
Data Strobe Timing
DQS, DQS differential READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS differential output high time
DQS, DQS differential output low time
DQS, DQS differential WRITE Preamble
DQS, DQS differential WRITE Postamble
DQS, DQS rising edge output access time from rising
CK, CK
DQS, DQS low-impedance time (Referenced from RL-
1)
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
DQS, DQS differential input low pulse width
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS,DQS falling edge setup time to CK, CK rising edge
DQS,DQS falling edge hold time to CK, CK rising edge
Command and Address Timing
DLL locking time
internal READ Command to PRECHARGE Command
delay
Delay from start of internal write transaction to internal
read command
WRITE recovery time
Mode Register Set command cycle time
Mode Register Set command update delay
CAS# to CAS# command delay
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period for 1KB page size
ACTIVE to ACTIVE command period for 2KB page size
Four activate window for 1KB page size
Four activate window for 2KB page size
Command and Address setup time to CK, CK refer-
enced to V
Command and Address hold time from CK, CK refer-
enced to V
Command and Address setup time to CK, CK refer-
enced to V
Control & Address Input pulse width for each input
Calibration Timing
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation short calibration time
IH
IH
IH
(AC) / V
(AC) / V
(AC) / V
IL
IL
IL
Parameter
(AC) levels
(AC) levels
(AC) levels
Speed
tDAL(min)
tHZ(DQS)
tLZ(DQS)
tIH(base)
tIH(base)
tIS(base)
tIS(base)
tIS(base)
tIS(base)
tDQSCK
tZQoper
Symbol
tWPRE
tRPRE
tWPST
tDQSH
tDQSS
tMPRR
AC160
AC175
DC100
AC135
AC150
tZQinitI
tZQCS
tRPST
tDQSL
tDLLK
tQSH
tWTR
tMRD
tMOD
tCCD
tRRD
tRRD
tFAW
tFAW
DC90
tQSL
tDSS
tDSH
tRTP
tRAS
tIPW
tWR
(12nCK,15ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,10ns)
(4nCK,10ns)
-0.25
-400
-800
MIN
0.38
0.38
0.45
0.45
max
max
max
max
max
512
215
200
285
275
365
350
900
512
256
0.9
0.3
0.9
0.3
0.2
0.2
15
40
50
64
4
4
1
-
DDR3-800
datasheet
Note 19
Note 11
See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin”
MAX
0.55
0.55
0.25
400
400
400
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(12nCK,15ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,10ns)
- 32 -
-0.25
0.38
0.38
-300
-600
0.45
0.45
37.5
MIN
max
max
max
max
max
512
140
125
210
200
290
275
780
512
256
0.9
0.3
0.9
0.3
0.2
0.2
15
50
64
4
4
1
-
DDR3-1066
WR + roundup (tRP / tCK(AVG))
Note 19
Note 11
MAX
0.55
0.55
0.25
300
300
300
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(12nCK,15ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
1.35V
1.35V
1.35V
(4nCK,6ns)
1.5V
1.5V
1.5V
-0.25
-255
-500
0.45
0.45
MIN
max
max
max
max
max
512
150
140
205
190
620
512
256
0.9
0.3
0.4
0.4
0.9
0.3
0.2
0.2
15
30
45
80
65
64
4
4
1
-
DDR3-1333
Note 19
Note 11
MAX
0.55
0.55
0.25
255
250
250
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(12nCK,15ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,6ns)
-0.27
MIN
-225
-450
0.45
0.45
0.18
0.18
max
max
max
max
max
512
130
120
185
170
560
512
256
0.9
0.3
0.4
0.4
0.9
0.3
15
30
40
60
45
64
4
4
1
-
DDR3L SDRAM
DDR3-1600
Note 19
Note 11
MAX
0.55
0.55
0.27
225
225
225
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Units
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
Rev. 1.0
13, 19, g
11, 13, b
12,13,14
b,16,27
b,16,27
13,14,f
NOTE
29, 31
30, 31
13, g
13, g
c, 32
c, 32
e,18
b,16
b,16
b,16
b,16
13,f
22
28
23
e
e
e
e
e
e
e
c