M471B5773DH0-YK0 Samsung Semiconductor, M471B5773DH0-YK0 Datasheet - Page 3

• Manufacturer Part Number: M471B5773DH0-YK0
• Manufacturer: Samsung Semiconductor

Specifications of M471B5773DH0-YK0

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Unbuffered SODIMM
Table Of Contents
2Gb D-die DDR3L SDRAM
1. DDR3L Unbuffered SODIMM Ordering Information...................................................................................................... 4
2. Key Features................................................................................................................................................................. 4
3. Address Configuration .................................................................................................................................................. 4
4. x64 DIMM Pin Configurations (Front side/Back Side)................................................................................................... 5
5. Pin Description ............................................................................................................................................................. 6
6. Input/Output Functional Description.............................................................................................................................. 8
7. Function Block Diagram: ............................................................................................................................................... 9
8. Absolute Maximum Ratings .......................................................................................................................................... 11
9. AC & DC Operating Conditions..................................................................................................................................... 11
10. AC & DC Input Measurement Levels .......................................................................................................................... 12
11. AC & DC Output Measurement Levels ....................................................................................................................... 19
12. IDD specification definition.......................................................................................................................................... 22
13. IDD SPEC Table ......................................................................................................................................................... 24
14. Input/Output Capacitance ........................................................................................................................................... 25
15. Electrical Characteristics and AC timing ..................................................................................................................... 26
16. Timing Parameters by Speed Grade .......................................................................................................................... 31
17. Physical Dimensions : ................................................................................................................................................. 36
7.1 2GB, 256Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ..................................................................... 9
7.2 4GB, 512Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................................... 10
8.1 Absolute Maximum DC Ratings............................................................................................................................... 11
8.2 DRAM Component Operating Temperature Range ................................................................................................ 11
9.1 Recommended DC Operating Conditions (SSTL-15).............................................................................................. 11
10.1 AC & DC Logic Input Levels for Single-ended Signals .......................................................................................... 12
10.2 V
10.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 15
10.4 Slew Rate Definition for Single Ended Input Signals............................................................................................. 19
10.5 Slew rate definition for Differential Input Signals ................................................................................................... 19
11.1 Single Ended AC and DC Output Levels ............................................................................................................... 19
11.2 Differential AC and DC Output Levels ................................................................................................................... 19
11.3 Single-ended Output Slew Rate ............................................................................................................................ 20
11.4 Differential Output Slew Rate ................................................................................................................................ 21
15.1 Refresh Parameters by Device Density................................................................................................................. 26
15.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 26
15.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 26
16.1 Jitter Notes ............................................................................................................................................................ 34
16.2 Timing Parameter Notes........................................................................................................................................ 35
17.1 256Mbx8 based 256Mx64 Module (1 Rank) - M471B5773DHS ........................................................................... 36
17.2 256Mbx8 based 512Mx64 Module (2 Ranks) - M471B5273DH0 .......................................................................... 37
10.3.1. Differential Signals Definition ......................................................................................................................... 15
10.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. 15
10.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 17
10.3.4. Differential Input Cross Point Voltage ............................................................................................................ 18
15.3.1. Speed Bin Table Notes .................................................................................................................................. 30
REF
Tolerances.................................................................................................................................................... 14
datasheet
- 3 -
DDR3L SDRAM
Rev. 1.0