M471B5773DH0-YK0 Samsung Semiconductor, M471B5773DH0-YK0 Datasheet - Page 7

• Manufacturer Part Number: M471B5773DH0-YK0
• Manufacturer: Samsung Semiconductor

Specifications of M471B5773DH0-YK0

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Unbuffered SODIMM
6. Input/Output Functional Description
RAS, CAS, WE
DQS0-DQS7
DQS0-DQS7
V
ODT0-ODT1
CKE0-CKE1
DQ0-DQ63
DM0-DM7
DD
CK0-CK1
CK0-CK1
BA0-BA2
SA0-SA1
A13-A15
V
Symbol
A10/AP,
A12/BC
V
RESET
A0-A9,
S0-S1
TEST
REFDQ,
,V
REFCA
SDA
SCL
A11
V
SS
DDSPD,
Supply
Supply
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
I/O
The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and
falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read opera-
tions is synchronized to the input clock.
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks,
CKE low initiates the Power Down mode or the Self Refresh mode.
Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is
selected by S0; Rank 1 is selected by S1.
When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS, RAS, and WE define
the operation to be executed by the SDRAM.
Selects which DDR3 SDRAM internal bank of eight is activated.
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register.
During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of
CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the
cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke
autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-
BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle,
AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-
charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to pre-
charge.A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-the fly) will be
performed (HIGH, no burst chop; LOW, burst chopped)
Data Input/Output pins.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input
data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect.
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is
sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3
SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to
the crosspoint of respective DQS and DQS.
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
Reference voltage for SSTL15 inputs.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor. A resistor must be
connected from the SDA bus line to V
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
Address pins used to select the Serial Presence Detect and Temp sensor base address.
The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules
RESET In Active Low This signal resets the DDR3 SDRAM
datasheet
DDSPD
- 7 -
on the system planar to act as a pull up.
Function
DDR3L SDRAM
Rev. 1.0