CYNSE70128-66BGC Cypress Semiconductor Corp, CYNSE70128-66BGC Datasheet - Page 106

• Manufacturer Part Number: CYNSE70128-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-66BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

12.1
Table 12-1. SRAM Address
12.2
The remainder of this section describes SRAM Read and SRAM Write operations.
SRAM Read enables Read access to the off-chip SRAM containing associative data. The latency from the issuance of the Read
instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction and will be depend
on the value programmed for the TLSZ parameter in the device configuration register. The latency of the ACK from the Read
instruction is the same as the latency of the Search instruction to the SRAM address plus the HLAT programmed in the configu-
ration register.
device performing the access.
SRAM Write enables Write access to the off-chip SRAM containing associative data. The latency from the second cycle of the
Write instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction and will depend
on the TLSZ value parameter programmed in the device configuration register.
instruction can begin right after the previous command has ended.
12.3
SRAM Read enables Read access to the off-chip SRAM containing associative data. The latency from the issuance of the Read
instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction and will depend on
the TLSZ value parameter programmed in the device configuration register. The latency of the ACK from the Read instruction is
the same as the latency of the Search instruction to the SRAM address plus the HLAT programmed in the configuration register.
The following explains the SRAM Read operation in a table with only one device that has the following parameters: TLSZ = 00,
HLAT = 000, LRAM = 1, and LDEV = 1. Figure 12-1 shows the associated timing diagram. For the following description, the
selected device refers to the only device in the table because it is the only device to be accessed.
At the end of cycle 6, the selected device floats ACK in a three-state condition, and a new command can begin.
Document #: 38-02040 Rev. *F
• Cycle 1A: The host ASIC applies the Read instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the address,
• Cycle 1B: The host ASIC continues to apply the Read instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[71:0] and drives ACK from high-Z to low.
• Cycle 5: The selected device drives the Read address on SADR[23:0]; it also drives ACK high, CE_L low, and ALE_L low.
• Cycle 6: The selected device drives CE_L high, ALE_L high, the SADR bus, the DQ bus in a three-state condition, and ACK low.
with DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the
DQ[25:21] lines. During this cycle, the host ASIC also supplies SADR[23:21] on CMD[8:6].
address with DQ[20:19] set to 10 to select the SRAM address.
Indirect Access
Command
PIO Read
PIO Write
Search
Learn
Generating an SRAM BUS Address
SRAM PIO Access
SRAM Read with a Table of One Device
Note
. SRAM Read is a blocking operation—no new instruction can begin until the ACK is returned by the selected
SRAM Operation
Write/Read
Read
Read
Write
Write
C8
C8
C8
C8
C8
23
C7
C7
C7
C7
C7
22
C6
C6
C6
C6
C6
21
Note
. SRAM Write is a pipelined operation—new
[20:16]
ID[4:0]
ID[4:0]
ID[4:0]
ID[4:0]
ID[4:0]
CYNSE70128
Index[15:0]
ADR[15:0]
SSR[15:0]
NFA[15:0]
ADR15:0]
[15:0]
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