CYNSE70128-66BGC Cypress Semiconductor Corp, CYNSE70128-66BGC Datasheet - Page 49

• Manufacturer Part Number: CYNSE70128-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-66BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The following is the sequence of operation for a single 72-bit Search command (also refer to the “Command and Command
Parameters,” on page 22).
Note
and odd pair of GMRs selected for the compare must be programmed with the same value.
Document #: 38-02040 Rev. *F
CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 1, LDEV = 1.
Note: |(BHI[2:0)] stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
• Cycle A: The host ASIC drives the CMDV high and applies Search command code (10) on CMD[1:0] signals. {CMD[10],
• Cycle B: The host ASIC continues to drive the CMDV high and applies Search command (10) on CMD[1:0]. CMD[5:2] must
CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be
driven with the same bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven with the 72-
bit data to be compared. The CMD[2] signal must be driven to a logic 0.
be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ bus during cycles A
and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching
entry and the hit flag (see page 16 for the description of SSR[0:7]). The DQ[71:0] continues to carry the 72-bit data to be
compared.
. For 72-bit searches, the host ASIC must supply the same 72-bit data on DQ[71:0] during both cycles A and B and the even
Figure 10-25. Timing Diagram for Device Number 6 in Block Number 3 (Device 30 in Depth-Cascaded Table)
SADR[23:0]
CMD[10:2]
|(LHI[6:0])
CMD[1:0]
PHS_L
I(BHI[2:0])
LHO[1:0]
BHO[2:0]
CE_L
ALE_L
OE_L
CMDV
WE_L
CLK2X
SSV
SSF
DQ
0
0
0
1
0
0
0
0
0
0
cycle
Search1
1
A B A B A B A B
D1
01
cycle
Search2
2
D2
01
cycle
Search3
3
D3
01
cycle
4
Search4
D4
01
cycle
5
cycle
6
cycle
7
Search1
(Hit on
some
device
above.)
cycle
8
z
z
z
z
Search2 Search4
(Hit on
some
device
above.)
cycle
9
z
z
Search3
(Hit on
some
device
above.)
cycle
10
CYNSE70128
(Global
miss; this device
default
driver.)
1
0
0
1
0
Page 49 of 137