CYNSE70128-66BGC Cypress Semiconductor Corp, CYNSE70128-66BGC Datasheet - Page 122

• Manufacturer Part Number: CYNSE70128-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-66BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

13.0
CYNSE70128 has two separate power supplies, one for the core (V
13.1
Proper power-up sequence is required to correctly initialize the Cypress NSEs before functional access to the device can begin.
RST_L and TRST_L should be held low before the power supplies ramp-up. RST_L must be set low for a duration of time
afterward and then set high. The following steps describe the proper power-up sequence.
Document #: 38-02040 Rev. *F
1. Set RST_L and TRST_L low.
2. Power up V
3. RST_L should be held low for 0.5ms (PLL lock time requirement). In CLK1X mode, the counting starts on the first rising edge
4. Continue to hold RST_L low for a minimum of 32 CLK1X cycles (when operating in CLK1X mode) or 64 CLK2X cycles (when
5. PHS_L does not need to be running during the reset. Also if JTAG is not used, TRST_L does not need to transition HIGH but
CLK2X mode. The order in which these signals (including V
of CLK1X after both V
rising edge of CLK2X when PHS_L is high, after both V
operating in CLK2X mode). Set RST_L to high afterward to complete the power-up sequence. For JTAG reset, TRST_L can
be brought high after V
instead can be held low. Figure 13-1 and Figure 13-2 illustrate the proper sequences of the power-up operation
Power-up Sequence
Power
DD
, V
DDQ
and start running CLK1X when operating in CLK1X mode or CLK2X and PHS_L when operating in
DD
DD
PHS_L
and V
CLK2x
and V
TRST_L
VDDQ
RST_L
VDD
DDQ
DDQ
VDDQ
CLK1x
VDD
TRST_L
have reached their steady state voltages. In CLK2X mode, the counting starts on the first
RST_L
have both reached their steady state voltages.
Figure 13-1. Power-up Sequence (CLK2x)
Figure 13-2. Power-up Sequence (CLK1x)
PLL lock time, 0.5ms
PLL lock time, 0.5ms
DD
and V
DD
and V
DDQ
DD
) and another for the I/Os (V
DDQ
have reached their steady state voltages.
) are applied is not critical.
64 CLK2x
64 CLK2x
cycles
cycles
DDQ
).
CYNSE70128
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