CYNSE70128-66BGC Cypress Semiconductor Corp, CYNSE70128-66BGC Datasheet - Page 26

• Manufacturer Part Number: CYNSE70128-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-66BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 10-7. Write Address Format for Data Array, Mask Array or SRAM (Single Write)
a
Table 10-8. Write Address Format for Internal Registers
Figure 10-4 shows the timing diagram of a burst Write operation of the data or mask array.
The burst Write operation lasts for (n + 2) CLK cycles. n signifies the number of accesses in the burst as specified in the BLEN
field of the WBURREG register. The following is the block Write operation sequence. This operation assumes that the host ASIC
has programmed the WBURREG with the starting address (ADR) and the length of transfer (BLEN) before initiating a burst Write
command.
Note:
Document #: 38-02040 Rev. *F
DQ[71:30]
12. “|” stands for logical OR operation. “{}” stands for concatenation operator.
Reserved
Reserved
Reserved
• Cycle 1A: The host ASIC applies the Write instruction to the CMD[1:0] (CMD[2] = 1), using CMDV = 1 and the address supplied
• Cycle 1B: The host ASIC continues to apply the Write instruction on the CMD[1:0] (CMD[2] = 1), using CMDV = 1 and the
• Cycle 2: The host ASIC drives the DQ[71:0] with the data to be written to the data or mask array location of the selected device.
on the DQ bus, as shown in Table 10-9. The host ASIC also supplies the GMR Index to mask the Write to the data or mask
array locations in {CMD[10], CMD[5:3]}. The host ASIC sets CMD[9] to 0 for the normal Write.
address supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask
array locations in {CMD[10], CMD[5:3]}. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21] lines. It
selects all the devices when DQ[25:21] = 11111.
The CYNSE70128 writes the data from the DQ[71:0] bus only to the subfield that has the corresponding mask bit set to 1 in
the GMR specified by the index {CMD[10],CMD[5:3]} supplied in cycle 1.
DQ[71:26]
Reserved
1: Indirect
1: Indirect
1: Indirect
0: Direct
0: Direct
0: Direct
DQ[29]
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
CMDV
EOT
DQ
SSR (appli-
cable if DQ[29]
is indirect)
SSR (appli-
cable if DQ[29]
is indirect)
SSR (appli-
cable if DQ[29]
is indirect)
DQ[28:26]
DQ[25:21]
Figure 10-4. Burst Write of the Data and Mask Arrays (BLEN = 4)
ID
DQ[25:21]
ID
ID
ID
Address
cycle
A
Write
1
01: Mask Array Reserved If DQ[29] is 0, this field carries the address of
00: Data Array Reserved If DQ[29] is 0, this field carries the address of
11: Register
B
DQ[20:19]
10: External
DQ[20:19]
cycle
SRAM
2
Data0 Data1 Data2
cycle
3
DQ[18:16]
Reserved If DQ[29] is 0, this field carries the address of
cycle
4
Reserved
DQ[18:7]
cycle
the data array location.
If DQ[29] is 1, the SSR specified on DQ[28:26]
is used to generate the address of data array
location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] |
DQ[0]} [Figure 10-4].
the mask array location.
If DQ[29] is 1, the SSR specified on DQ[28:26]
is used to generate the address of the mask
array location: {SSR[15:2], SSR[1] | DQ[1],
SSR[0] | DQ[0]} [Figure 10-4].
the SRAM location.
If DQ[29] is 1, the SSR specified on DQ[28:26]
is used to generate the address of SRAM
location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] |
DQ[0]} [Figure 10-4].
5
Data3
cycle
6
X
DQ[15:0]
Register address
[12]
CYNSE70128
DQ[6:0]
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