CYNSE70128-66BGC Cypress Semiconductor Corp, CYNSE70128-66BGC Datasheet - Page 23

• Manufacturer Part Number: CYNSE70128-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-66BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 10-3. Read Command Parameters
The single Read operation takes six clock cycles, in the following sequence.
At the termination of cycle 6, the selected device releases the ACK line to three-state condition. The Read instruction is complete,
and a new operation can begin.
PIO Access” on page 106). Table 10-4 lists and describes the format of the Read address for a data array, mask array, or SRAM.
Document #: 38-02040 Rev. *F
Table 10-4. Read Address Format for Data Array, Mask Array, or SRAM
CMD Parameter CMD[2] Read Command
Note:
• Cycle 1: The host ASIC applies the Read instruction on the CMD[1:0] (CMD[2]= 0) using CMDV = 1 and the DQ bus supplies
• Cycle 2: The host ASIC floats DQ[71:0] to three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in three-state condition.
• Cycle 4: The selected device starts to drive the DQ[71:0] bus, and drives the ACK signal from Z to LOW.
• Cycle 5: The selected device drives the read data from the addressed location on the DQ[71:0] bus, and drives the ACK signal
• Cycle 6: The selected device floats the DQ[71:0] to three-state condition and drives the ACK signal LOW.
11. “|” stands for logical OR operation. “{}” stands for concatenation operator.
DQ[71:30]
Reserved
the address, as shown in Table 10-4 and Table 10-5. The host ASIC selects the CYNSE70128 for which ID[4:0] matches the
DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the CYNSE70128 with the LDEV bit set. The host ASIC also
supplies SADR[23:21] on CMD[8:6] in cycle A of the Read instruction if the Read is directed to the external SRAM.
HIGH.
0
1
1: Indirect
0: Direct
DQ[29]
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
CMDV
ACK
DQ
Successful
Search Register
Index (appli-
cable if DQ[29]
is indirect)
DQ[28:26]
Single Read
Burst Read
Note
. The latency of the SRAM Read will be different than the one described above (see “SRAM
Figure 10-1. Single-Location Read Cycle Timing
DQ[25:21] DQ[20:19] DQ[18:16]
cycle
A
Address
1
Read
Reads a single location of the data array, mask array, external SRAM, or device
registers. All access information is applied on the DQ bus.
Reads a block of locations from the data array, or mask array as a burst. The
internal register (RBURADR) specifies the starting address and the length of the
data transfer from the data or mask array, and it auto-increments the address for
each access. All other access information is applied on the DQ bus.
device registers and external SRAM can only be read in single-Read mode.
ID
B
cycle
2
00: Data
Array
cycle
3
Reserved If DQ[29] is 0, this field carries the address of
cycle
4
FF
the data array location. If DQ[29] is 1, the SSRI
specified on DQ[28:26] is used to generate the
address of the data array location: {SSR[15:2],
SSR[1] | DQ[1], SSR[0] | DQ[0]}.
Description
cycle
5
Data
cycle
6
DQ[15:0]
CYNSE70128
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[11]
Note
. The