CYNSE70128-66BGC Cypress Semiconductor Corp, CYNSE70128-66BGC Datasheet - Page 25

• Manufacturer Part Number: CYNSE70128-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-66BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 10-6. Read Address Format for Data and Mask Arrays
10.4
The Write can be a single Write of a data array, mask array, register, or external SRAM location (CMD[2] = 0). It can be a burst
Write (CMD[2] = 1) using an internal auto-incrementing address register (WBURADR) of the data or mask array locations.
A single-location Write is a three-cycle operation, as shown in Figure 10-3. The burst Write adds one extra cycle for each
successive location Write.
The following is the Write operation sequence, and Table shows the Write address format for the data array, the mask array, or
the single-Write SRAM. Table 10-8 shows the Write address format for the internal registers.
At the termination of cycle 3, another operation can begin.
described above (see “SRAM PIO Access” on page 106).
Document #: 38-02040 Rev. *F
• Cycle 1A: The host ASIC applies the Write instruction to the CMD[1:0] (CMD[2] = 0), using CMDV = 1 and the address supplied
• Cycle 1B:The host ASIC continues to apply the Write instruction to the CMD[1:0] (CMD[2] = 0), using CMDV = 1 and the
• Cycle 2: The host ASIC drives the DQ[71:0] with the data to be written to the data array, mask array, or register location of the
• Cycle 3: Idle cycle.
on the DQ bus. The host ASIC also supplies the GMR Index to mask the Write to the data or mask array location on
{CMD[10],CMD[5:3]}. For SRAM Writes, the host ASIC must supply the SADR[23:21] on CMD[8:6]. The host ASIC sets CMD[9]
to 0 for the normal Write.
address supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask
array locations in {CMD[10], CMD[5:3]}.The host ASIC selects the device where ID[4:0] matches the DQ[25:21] lines, or it
selects all the devices when DQ[25:21] = 11111.
selected device.
DQ[71:26]
Reserved
Reserved
Write Command
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
CMDV
DQ[25:21]
DQ
ID
ID
cycle 0
01: Mask Array
00: Data Array
DQ[20:19]
Figure 10-3. Single Write Cycle Timing
A
cycle 1
Address
Write
B
Note
DQ[18:16]
Reserved
Reserved
. The latency of the SRAM Write will be different than the one
cycle 2
Data
Do not care
register (RBURADR) which increments for each
access.
Do not care
register (RBURADR) which increments for each
access.
cycle 3
X
. These 16 bits come from the internal
. These 16 bits come from the internal
DQ[15:0]
cycle 4
CYNSE70128
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