ISL9N315AD3 Fairchild Semiconductor, ISL9N315AD3 Datasheet - Page 7

• Manufacturer Part Number: ISL9N315AD3
• Description: MOSFET Power N-Ch LL UltraFET PWM Optimized
• Manufacturer: Fairchild Semiconductor

Specifications of ISL9N315AD3

• Configuration: Single
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 0.028 Ohms
• Drain-source Breakdown Voltage: 30 V
• Gate-source Breakdown Voltage: +/- 20 V
• Continuous Drain Current: 30 A
• Power Dissipation: 55 W
• Maximum Operating Temperature: + 175 C
• Mounting Style: Through Hole
• Package / Case: TO-251
• Minimum Operating Temperature: - 55 C
• Lead Free Status / Rohs Status: Details

©2003 Fairchild Semiconductor Corporation
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
application.
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
2. The number of copper layers and the thickness of the
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are R
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
P
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. R
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
DM
R JA
P D M
whether there is copper on one side or both sides of the
board.
board.
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
.
=
=
-----------------------------
temperature
T
33.32
JM
Z J A
A
JA
–
JA
T
(
Therefore
+
o
A
is defined as the natural log of the area
for the device as a function of the top
C), and thermal resistance R
------------------------------------ -
0.268
23.84
or
+
Area
the
power
JA
application’s
JM
values listed in the
is never exceeded.
dissipation.
JM
, and the
JA
(EQ. 1)
(EQ. 2)
DM
ambient
(
o
, in an
Pulse
DM
C/W)
is
Figure 21. Thermal Resistance vs Mounting
125
100
75
50
25
0.01
AREA, TOP COPPER AREA (in
0.1
Pad Area
R
JA
= 33.32 + 23.84/(0.268+Area)
ISL9N315AD3/ISL9N315AD3ST Rev.A1
1
2
)
10