ST92T163R4T1 STMicroelectronics, ST92T163R4T1 Datasheet - Page 108

• Manufacturer Part Number: ST92T163R4T1
• Description: Microcontrollers (MCU) OTP EPROM 20K USB/I2
• Manufacturer: STMicroelectronics

Specifications of ST92T163R4T1

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: EPROM
• Program Memory Size: 20 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SCI, USB
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-64
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

ST92163 - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
8.1.4 WDT Interrupts
The Timer/Watchdog issues an interrupt request
at every End of Count, when this feature is ena-
bled.
A pair of control bits, IA0S (EIVR.1, Interrupt A0 se-
lection bit) and TLIS (EIVR.2, Top Level Input Se-
lection bit) allow the selection of 2 interrupt sources
(Timer/Watchdog End of Count, or External Pin)
handled in two different ways, as a Top Level Non
Maskable Interrupt (Software Reset), or as a
source for channel A0 of the external interrupt logic.
A block diagram of the interrupt logic is given in
Figure 3.
Note: Software traps can be generated by setting
the appropriate interrupt pending bit.
Table 1 below, shows all the possible configura-
tions of interrupt/reset sources which relate to the
Timer/Watchdog.
A reset caused by the watchdog will set bit 6,
WDGRES of R242 - Page 55 (Clock Flag Regis-
ter). See section CLOCK CONTROL REGIS-
TERS.
Table 19. Interrupt Configuration
Legend:
WDG = Watchdog function
SW TRAP = Software Trap
Note: If IA0S and TLIS = 0 (enabling the Watchdog EOC as interrupt source for both Top Level and INTA0
interrupts), only the INTA0 interrupt is taken into account.
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WDGEN
0
0
0
0
1
1
1
1
Control Bits
IA0S
0
0
1
1
0
0
1
1
TLIS
0
1
0
1
0
1
0
1
WDG/Ext Reset
WDG/Ext Reset
WDG/Ext Reset
WDG/Ext Reset
Ext Reset
Ext Reset
Ext Reset
Ext Reset
Reset
Enabled Sources
Figure 63. Interrupt Sources
INT0
NMI
SW TRAP
SW TRAP
Ext Pin
Ext Pin
Ext Pin
Ext Pin
INTA0
Timer
Timer
TIMER WATC HDOG
0
1
0
1
MUX
MUX
Top Level
SW TRAP
SW TRAP
Ext Pin
Ext Pin
Ext Pin
Ext Pin
Timer
Timer
TLIS (EIVR.2)
IA0S (EIVR .1)
WDGEN (WCR.6)
INTERRUP T REQUEST
RESET
INTA0 REQUEST
Operating Mode
TOP LEVEL
Watchdog
Watchdog
Watchdog
Watchdog
Timer
Timer
Timer
Timer
VA00293