PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 123

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

3.8.3.2
The transmission of transparent frames (XTF command) is shown in
For transparent frames, the whole frame including address and control field must be
written to the XFIFOD. The host configures whether the CRC is generated and
appended to the frame (default) or not (selected in EXMD.XCRC).
Further, the host selects the interframe time fill signal which is transmitted between
HDCL frames (EXMD.ITF). One option is to send continuous flags (’01111110’),
however if D-channel access handling (collision resolution on the S bus) is required, the
signal must be set to idle (continuous ’1’s are transmitted). Reprogramming of ITF takes
effect only after the transmission of the current frame has been completed or after an
XRES command.
Figure 65
3.8.4
By setting the enable HDLC data bits (D_EN_D, D_EN_B1, D_EN_B2) in the DCI_CR
register the HDLC controller can access the D, B1 and B2 channels or any combination
of them. In all modes (except extended transparent mode) transmission always works
frame aligned, i.e. it starts with the first selected channel, whereas reception searches
for a flag anywhere in the serial data stream.
Data Sheet
Transmit Transparent Frame
*
1)
Transmit Frame Structure
Access to IOM-2 channels
The CRC is generated by default.
If EXMR.XCRC is set no CRC is appended
Transmit Data Flow
(XTF)
FLAG
ADDRESS
ADDR
123
XFIFO
CONTROL DATA
CTRL
Description of Functional Blocks
I
CHECKRAM
CRC
*
1)
Figure
fifoflow_tran.vsd
FLAG
PSB 3186
PSF 3186
65.
2000-08-23