PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 150

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PSB3186FV1.4

Manufacturer Part Number
PSB3186FV1.4
Description
ISDN Interface ISDN
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB3186FV1.4

Control Type
HDLC
Data Rate
192 Kbps
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Package / Case
MQFP-64
Lead Free Status / Rohs Status
 Details
If this bit is set, the ISAC-SX TE will try to access the TIC-bus to occupy the C/I-channel
even if no D-channel frame has to be transmitted. It should be reset when the access
has been completed to grant a similar access to other devices transmitting in that IOM-
channel.
Note: Access is always granted by default to the ISAC-SX TE with TIC-Bus Address
4.1.20
Value after reset: FE
CIR1
CODR1 ... C/I-Code 1 Receive
CICW, CI1E ... C/I-Channel Width, C/I-Channel 1 Interrupt Enable
These two bits contain the read back values from CIX1 register (see below).
4.1.21
Value after reset: FE
CIX1
CODX1 ... C/I-Code 1 Transmit
Bits 7-2 of C/I-channel 1.
CICW... C/I-Channel Width
CICW selects between a 4 bit (’0’) and 6 bit (’1’) C/I1 channel width.
The C/I1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher
two bits are ignored for interrupt generation. However in write direction the full CODX1
code is transmitted, i.e. the host must write the higher two bits to “1”.
CI1E ... C/I-Channel 1 Interrupt Enable
Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled (1) or masked (0).
Data Sheet
(TBA2-0, STCR register) ’7’, which has the lowest priority in a bus configuration.
7
7
CIR1 - Command/Indication Receive 1
CIX1 - Command/Indication Transmit 1
H
H
CODR1
CODX1
150
Detailed Register Description
CICW CI1E
CICW CI1E
0
0
PSB 3186
PSF 3186
2000-08-23
WR (2F)
RD (2F)

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