SDKZSPF LSI, SDKZSPF Datasheet - Page 176

• Manufacturer Part Number: SDKZSPF
• Manufacturer: LSI

Specifications of SDKZSPF

• Lead Free Status / Rohs Status: Supplier Unconfirmed

8.2.40 show pipe
8-34
Format –
Example –
For zsimg2, you can use a symbol instead of the absolute address value.
This command shows the contents of all stages of the pipeline. An
instruction in the pipeline is represented in the following format:
(seqID) Address:Opcode:IssueBit:Disassembled
instructions,
where:
For zsim400, the output displays a five-stage pipeline
CYCLE: 0
stage(#:#): five stages of the execution pipeline are identified with a
single letter – F (Fetch/decode), G (Group), R (Read), E (Execute), and
W (Write Back) – followed by two integers representing the number of
instructions currently in that stage and the number of instructions that
advance to the next stage in the following cycle.
ZSP SDK Cycle-Accurate Simulator
Copyright © 1999-2003 by LSI Logic Corporation. All rights reserved.
------------------------------------------ F(0:0)
------------------------------------------ G(0:0)
------------------------------------------ R(0:0)
------------------------------------------ E(0:0)
------------------------------------------ W(0:0)
show imem {int|ext} [addr] [size]
zsim{1} show imem int 0xf000 0x10
zsim{1} show imem int foo_function 20
SeqID: Unique ascending sequence number for each instruction.
Address: Address of the instruction in memory.
Opcode: Binary opcode of an instruction in hexadecimal digit.
IssueBit: Instruction is issued to the next stage in the following cycle.