SDKZSPF LSI, SDKZSPF Datasheet - Page 184

• Manufacturer Part Number: SDKZSPF
• Manufacturer: LSI

Specifications of SDKZSPF

• Lead Free Status / Rohs Status: Supplier Unconfirmed

UL - D$[14]: ------ I ------ ------ ------ ------
UL - D$[15]: ------ I ------ ------ ------ ------
UL - D$[16]: ------ I ------ ------ ------ ------
zsim{6}> run 4 ; show pipe
CYCLE=000004 PC=0x2000
CYCLE: 4
zsim{7}> show icache
I$[0]: 0x2000 V 0x2cfb V 0x3cf7 V 0xa6d0 V 0x2460
I$[1]: 0x2004 V 0x3400 V 0xbc54 V 0xa051 V 0x6054
I$[2]: ------ I ------ I ------ I ------ I ------
I$[3]: ------ I ------ I ------ I ------ I ------
I$[4]: ------ I ------ I ------ I ------ I ------
I$[5]: ------ I ------ I ------ I ------ I ------
I$[6]: ------ I ------ I ------ I ------ I ------
I$[7]: ------ I ------ I ------ I ------ I ------
zsim{8}> _
zsim{8}> set break sym main
Breakpoint 1 on PC at address 0x2010 of main
zsim{9}> enable trace write
***(info) Instruction trace is ON.
zsim{10}> run
8-42
------------------------------------------ F(4:1)
(7)2007:6054:0:st
(6)2006:a051:0:add
(5)2005:bc54:0:mov
(4)2004:3400:1:movh
------------------------------------------ G(4:1)
(3)2003:2460:0:movl
(2)2002:a6d0:0:mov
(1)2001:3cf7:0:movh
(0)2000:2cfb:1:movl
------------------------------------------ R(0:0)
------------------------------------------ E(0:0)
------------------------------------------ W(0:0)
The 17 lines of the data cache are shown to be empty in the above
example. The first column contains the address (four word boundary)
and the remaining four columns contain data values. An ‘I’ to the left of
a data line indicates that the corresponding data line is invalid.
Continuing with the example, as execution proceeds, the pipeline and
instruction cache reflect changes expected by instruction flow:
The simulator output following demonstrates the use of the PC
breakpoint. A breakpoint is set for address 0x10 and the simulator is
advanced. Execution halts when the instruction associated with the
breakpoint address reaches the Group stage. The state of the pipeline
and operand registers are shown after the breakpoint halt occurs.
ZSP SDK Cycle-Accurate Simulator
Copyright © 1999-2003 by LSI Logic Corporation. All rights reserved.
r5, r4, 0
r5, 0x1
r5, r4
r4, 0x0
r4, 0x60
r13, 0x0
r12, 0xf7
r12, 0xfb