SDKZSPF LSI, SDKZSPF Datasheet - Page 177

• Manufacturer Part Number: SDKZSPF
• Manufacturer: LSI

Specifications of SDKZSPF

• Lead Free Status / Rohs Status: Supplier Unconfirmed

For zsimg2, the output displays an eight-stage pipeline.
CYCLE: 0 <stall>
stage(#:#): eight stages of the execution pipeline are identified with
double letters – FD (Fetch/decode), GR (Group), RD (Read), AG
(Address Generation), M0 (Memory stage 0), M1 (Memory Stage 1), EX
(Execute), and WB (Write Back) – followed by two integers representing
the number of instructions currently in that stage and the number of
instructions that advance to the next stage in the following cycle.
The <stall> field next to the cycle number indicates a stall has occurred
in the current cycle.
Table 8.11
Format –
Example –
ZSIM Commands
Copyright © 1999-2003 by LSI Logic Corporation. All rights reserved.
Stall
Pipe stalls by instruction #
Half pipe stalls AG
Half pipe stalls M0
------------------------------------------ FD(0:0)
------------------------------------------ GR(0:0)
------------------------------------------ RD(0:0)
------------------------------------------ AG(0:0)
------------------------------------------ M0(0:0)
------------------------------------------ M1(0:0)
------------------------------------------ EX(0:0)
------------------------------------------ WB(0:0)
------------------------------------------ F(4:2)
(13)000d:5448:0:mac2.a
(12)000c:788f:0:lddu
(11)000b:784e:1:lddu
(10)000a:9a00:1:xor.e
------------------------------------------ G(4:2)
show pipe
zsim{32} show pipe
CYCLE: 8
Pipe Stall Description
Table 8.11
Description
Full pipe stall occurs by the indicated
instruction number.
Pipe stalls from AG and up.
Pipe stalls from M0 and up.
shows all three possible stalls for G2.
r4.e, r8.e
r8.e, r15, 2
r4.e, r14, 2
r0.e, r0.e
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