LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 206
LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Memory Modules
Single Port RAM (RAM_DQ) – EBR Based
The EBR blocks in the LatticeECP/EC and LatticeXP devices can be configured as Single Port RAM or RAM_DQ.
IPexpress allows users to generate the Verilog-HDL or VHDL along an EDIF netlist for the memory size as per the
design requirements.
IPexpress generates the memory module as shown in Figure 9-7.
Figure 9-7. Single Port Memory Module generated by IPexpress
Since the device has a number of EBR blocks, the generated module makes use of these EBR blocks or primitives
and cascades them to create the memory sizes specified by the user in the IPexpress GUI. For memory sizes
smaller than an EBR block, the module will be created in one EBR block. In cases where the specified memory is
larger than one EBR block, multiple EBR block can be cascaded, in depth or width (as required to create these
sizes).
The memory primitive for RAM_DQ for LatticeECP/EC and LatticeXP devices is shown in Figure 9-8.
Figure 9-8. Single Port RAM Primitive or RAM_DQ for LatticeECP/EC and LatticeXP Devices
In Single Port RAM mode the input data and address for the ports are registered at the input of the memory array.
The output data of the memory is optionally registered.
AD[x:0]
CS[2:0]
DI[y:0]
RST
CLK
ClockEn
WE
Address
CE
Reset
Clock
Data
WE
EBR-based Single Port
EBR
9-7
RAM_DQ
Memory
LatticeECP/EC and LatticeXP Devices
DO[y:0]
Q
Memory Usage Guide
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