LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 9

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Lattice Semiconductor Design Floorplanning
Lattice Semiconductor FPGA Successful Place and Route
HDL Design with Lattice Semiconductor FPGA Devices ................................................................................. 16-8
Technical Support Assistance........................................................................................................................ 16-17
Introduction ...................................................................................................................................................... 17-1
Supported Architectures................................................................................................................................... 17-1
Related Documentation.................................................................................................................................... 17-1
Floorplanning Definition ................................................................................................................................... 17-1
Complex FPGA Design Management .............................................................................................................. 17-1
Floorplanning Design Flow............................................................................................................................... 17-2
When to Floorplan............................................................................................................................................ 17-2
Floorplan to Improve Design Performance ...................................................................................................... 17-3
Floorplan to Preserve Module Performance .................................................................................................... 17-3
Floorplan for Design Reuse ............................................................................................................................. 17-3
How to Floorplan a Design............................................................................................................................... 17-4
Special Floorplanning Considerations.............................................................................................................. 17-7
Summary.......................................................................................................................................................... 17-7
Technical Support Assistance.......................................................................................................................... 17-8
Introduction ...................................................................................................................................................... 18-1
ispLEVER Place and Route Software (PAR) ................................................................................................... 18-1
General Strategy Guidelines ............................................................................................................................ 18-2
Analyzing Timing Reports ................................................................................................................................ 18-6
ispLEVER Controlled Place and Route.......................................................................................................... 18-10
Guided Map and PAR .................................................................................................................................... 18-14
Lattice Semiconductor FPGA Synthesis Library ..................................................................................... 16-8
Implementing Multiplexers .................................................................................................................... 16-10
Clock Dividers ....................................................................................................................................... 16-10
Register Control Signals ....................................................................................................................... 16-12
Use PIC Features.................................................................................................................................. 16-14
Implementation of Memories................................................................................................................. 16-16
Preventing Logic Replication and Limited Fanout................................................................................. 16-16
Use ispLEVER Project Navigator Results for Device Utilization and Performance .............................. 16-17
Design Performance Enhancement Strategies ....................................................................................... 17-4
Design Floorplanning Methodologies...................................................................................................... 17-4
When to use PGROUP vs. UGROUP ..................................................................................................... 17-4
Floorplanner GUI Usage ......................................................................................................................... 17-6
Embedded Block RAM Placement .......................................................................................................... 17-7
I/O Grouping............................................................................................................................................ 17-7
Large Module Grouping .......................................................................................................................... 17-7
Carry Chains and Bus Grouping ............................................................................................................. 17-7
SLICs in Groups...................................................................................................................................... 17-7
Placement ............................................................................................................................................... 18-1
Routing.................................................................................................................................................... 18-1
Timing Driven PAR Process.................................................................................................................... 18-2
Typical Design Preferences .................................................................................................................... 18-2
Proper Preferences ................................................................................................................................. 18-3
Translating Board Requirements into FPGA Preferences ...................................................................... 18-4
Example 1. Multicycle Between Two Different Clocks ............................................................................ 18-6
Example 2. CLOCK_TO_OUT with PLL Feedback................................................................................. 18-8
Running Multiple Routing Passes ......................................................................................................... 18-10
Using Multiple Placement Iterations (Cost Tables) ............................................................................... 18-11
Clock Boosting ...................................................................................................................................... 18-12
Notes on Guided Mapping .................................................................................................................... 18-15
Notes on Guided PAR........................................................................................................................... 18-15
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LatticeECP/EC Family Data Sheet
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