LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 245

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Figure 9-54. PFU Based Distributed Single Port RAM Timing Waveform – with Output Registers
Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based
PFU-based Distributed Dual Port RAM is also created using the four input LUT (Look-Up Table) available in the
PFU. These LUTs can be cascaded to create larger distributed memory sizes.
Figure 9-55 shows the Distributed Single Port RAM module as generated by IPexpress.
Figure 9-55. Distributed Dual Port RAM Module Generated by IPexpress
The generated module makes use of a 4-input LUT available in the PFU. Additional logic for Clocks, Clock Enables
and Reset is generated by utilizing the resources available in the PFU. The basic Distributed Dual Port RAM primi-
tive for the LatticeECP/EC and LatticeXP devices is shown in Figure 9-56.
ClockEn
Address
Reset
Clock
Data
WE
Q
t
t
SUWREN_PFU
SUADDR_PFU
t
SUDATA_PFU
Data_0
Add_0
RdClockEn
WrClockEn
WrAddress
RdAddress
t
t
HADDR_PFU
HDATA_PFU
RdClock
WrClock
Invalid Data
Reset
Data
WE
Data_1
Add_1
t
HWREN_PFU
Distributed Dual Port
9-46
PFU based
Memory
Add_0
LatticeECP/EC and LatticeXP Devices
t
CO?
Data_0
Add_1
Q
Memory Usage Guide
Data_1
Add_2
Data_2