LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 403

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Also note that the PGROUP attribute can be placed on multiple instantiations of modules (e.g. VHDL generate
statements) and each instantiation will have its own PGROUP. Using a UGROUP will not work in this case.
In Figures 3 and 4, the arrows represent control and data paths where there is interaction between different levels
of hierarchy. The thick lined arrow represents the critical path where the design is failing to make performance.
Figure 16-3. PGROUP Same Hierarchy Example, PGROUP CONTROLLER
Figure 16-3 illustrates a design hierarchy where the failing paths are the connections between COUNTER and
STATE_MACHINE design blocks. The easiest implementation for this example is to PGROUP the CONTROLLER,
which is the module in which the COUNTER and STATE_MACHINE are instantiated within.
For example, if the following Synplify attribute is in the Verilog HDL file:
then the COUNTER and STATE_MACHINE will be grouped in the FPGA inside a boundary box. Now assume that
the COUNTER is mapped into PFU_0 and PFU_1 and the STATE_MACHINE is mapped into PFU_2. The resulting
preference generated by map in the .prf file will be:
Notice the TOP/ hierarchy is prepended to the CONTROLLER PGROUP identifier.
Figure 16-4. UGROUP Different Hierarchy Example, UGROUP REGISTER_FILE and STATE MACHINE
Figure 16-4 shows an example design hierarchy where the failing paths are the connections between
REGISTER_FILE and STATE_MACHINE modules. The simplest thing to do here is to UGROUP the
REGISTER_FILE and STATE_MACHINE together.
For example, if the following Synplify attributes are in the Verilog HDL file:
PGROUP “TOP/CONTROLLER/CONTROL_GROUP”
module CONTROLLER (<port_list>)/* synthesis pgroup=”CONTROL_GROUP” */;
Top level
of hierarchy
Second level
of hierarchy
Third level
of hierarchy
Top level
of hierarchy
Second level
of hierarchy
Third level
of hierarchy
COMP “PFU_0”
COMP “PFU_1”
COMP “PFU_2”;
COUNTER
COUNTER
16-5
Lattice Semiconductor Design Floorplanning
CONTROLLER
CONTROLLER
critical
TOP
TOP
path
STATE_MACHINE
STATE_MACHINE
REGISTER_FILE
REGISTER_FILE
critical
path