SAK-C167CS-L33M Infineon Technologies, SAK-C167CS-L33M Datasheet - Page 21
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SAK-C167CS-L33M
Manufacturer Part Number
SAK-C167CS-L33M
Description
Manufacturer
Infineon Technologies
Datasheet
1.SAK-C167CS-L33M.pdf
(81 pages)
Specifications of SAK-C167CS-L33M
Cpu Family
C166
Device Core Size
16b
Frequency (max)
33MHz
Interface Type
CAN/SPI/USART
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
11KB
# I/os (max)
111
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
24-chx10-bit
Instruction Set Architecture
CISC/RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
MQFP
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SAK-C167CS-L33M
Manufacturer:
HITACHI
Quantity:
6 220
Company:
Part Number:
SAK-C167CS-L33M CA+
Manufacturer:
Infineon Technologies
Quantity:
10 000
Note: When one or both of the on-chip CAN Modules are used with the interface lines
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C167CS’s instructions can be
executed in just one machine cycle which requires 50 ns at 40 MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 ×
16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline
optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 4
Data Sheet
ROM
assigned to Port 4, the CAN lines override the segment address lines and the
segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines
A21/A19 … A16. CS lines can be used to increase the total amount of
addressable external memory.
CPU Block Diagram
32
Data Page Ptr.
Exec. Unit
Instr. Reg.
SYSCON
Instr. Ptr.
BUSCON 1
BUSCON 0
BUSCON 2
BUSCON 3
BUSCON 4
STKUN
STKOV
PSW
SP
Pipeline
4-Stage
Barrel - Shifter
Bit-Mask Gen
Code Seg. Ptr.
Mul/Div-HW
Context Ptr.
ADDRSEL 1
ADDRSEL 3
ADDRSEL 4
ADDRSEL 2
ALU
MDH
MDL
CPU
17
(16-bit)
Registers
Purpose
General
R15
R0
16
16
C167CS-4R
V2.2, 2001-08
C167CS-L
Internal
RAM
R15
R0
MCB02147