MC68HC711E9FU Freescale Semiconductor, MC68HC711E9FU Datasheet - Page 88
MC68HC711E9FU
Manufacturer Part Number
MC68HC711E9FU
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC711E9FU.pdf
(242 pages)
Specifications of MC68HC711E9FU
Cpu Family
HC11
Device Core Size
8b
Frequency (max)
4MHz
Interface Type
SCI/SPI
Program Memory Type
EPROM
Program Memory Size
12KB
Total Internal Ram Size
512Byte
# I/os (max)
38
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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Resets and Interrupts
5.5.1 Interrupt Recognition and Register Stacking
An interrupt can be recognized at any time after it is enabled by its local mask, if any, and by the global
mask bit in the CCR. Once an interrupt source is recognized, the CPU responds at the completion of the
instruction being executed. Interrupt latency varies according to the number of cycles required to
complete the current instruction. When the CPU begins to service an interrupt, the contents of the CPU
registers are pushed onto the stack in the order shown in
I bit and the X bit, if XIRQ is pending, are set to inhibit further interrupts. The interrupt vector for the highest
priority pending source is fetched and execution continues at the address specified by the vector. At the
88
FFC0, C1 – FFD4, D5 Reserved
Vector Address
FFDC, DD
FFDA, DB
FFDE, DF
FFEC, ED
FFD6, D7
FFD8, D9
FFEA, EB
FFEE, EF
FFFC, FD
FFE0, E1
FFE2, E3
FFE4, E5
FFE6, E7
FFE8, E9
FFFA, FB
FFFE, FF
FFF0, F1
FFF2, F3
FFF4, F5
FFF6, F7
FFF8, F9
Table 5-4. Interrupt and Reset Vector Assignments
SCI serial system
SPI serial transfer complete
Pulse accumulator input edge
Pulse accumulator overflow
Timer overflow
Timer input capture 4/output compare 5
Timer output compare 4
Timer output compare 3
Timer output compare 2
Timer output compare 1
Timer input capture 3
Timer input capture 2
Timer input capture 1
Real-time interrupt
IRQ (external pin)
XIRQ pin
Software interrupt
Illegal opcode trap
COP failure
Clock monitor fail
RESET
• SCI receive data register full
• SCI receiver overrun
• SCI transmit data register empty
• SCI transmit complete
• SCI idle line detect
M68HC11E Family Data Sheet, Rev. 5.1
Interrupt Source
Table
5-5. After the CCR value is stacked, the
Mask Bit
None
None
None
None
None
CCR
—
X
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Freescale Semiconductor
NOCOP
PAOVI
I4/O5I
Local
Mask
None
None
None
None
None
TCIE
SPIE
OC4I
OC3I
OC2I
OC1I
CME
IC3I
IC2I
IC1I
RTII
ILIE
PAII
RIE
RIE
TOI
TIE
—
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