MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 176

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

generates the vector number, which is the sum of the interrupt priority level plus 24 ($18).
There are seven distinct autovectors that can be used, corresponding to the seven levels
of interrupts available with IPL2–IPL0 signals. Figure 7-23 illustrates a functional timing
diagram for an autovector operation.
7.5.1.3 SPURIOUS INTERRUPT ACKNOWLEDGE BUS CYCLE. When a device does
not respond to an interrupt acknowledge bus cycle with TA, or AVEC and TA, the external
logic typically returns the transfer error acknowledge signal (TEA). In this case, the
M68040 automatically generates the spurious interrupt vector number 24 ($18) instead of
the interrupt vector number. If TA and TEA are both asserted, the processor retries the
cycle.
7-34
Figure 7-23. Autovector Interrupt Acknowledge Bus Cycle Timing
UPA1, UPA0
TM2–TM0
TT1, TT0
D31–D0
A31–A0
CIOUT
AVEC
BCLK
SIZ0
SIZ1
R/W
Freescale Semiconductor, Inc.
TIP
TS
TA
For More Information On This Product,
AUTOVECTORED
ACKNOWLEDGE
C1
INTERRUPT
M68040 USER’S MANUAL
Go to: www.freescale.com
BYTE
C2
INTERRUPT LEVEL
C1
WRITE STACK
C2
MOTOROLA