MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 191

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

In addition to the indeterminate condition, the external arbiter’s design needs to include
the function of BR. For example, in certain cases associated with conditional branches,
the M68040 can assert BR to request the bus from an alternate bus master, then negate
BR without using the bus, regardless of whether or not the external arbiter eventually
asserts BG. This situation happens when the M68040 attempts to prefetch an instruction
for a conditional branch. To achieve maximum performance, the processor prefetches the
instructions of both paths for a conditional branch. If the conditional branch results in a
branch-not-taken, the previously issued branch-taken prefetch is then terminated since the
prefetch is no longer needed. In an attempt to save time, the M68040 negates BR. If BG
takes too long to assert, the M68040 enters a disregard request condition.
The BR signal can be reasserted immediately for a different pending bus request, or it can
stay negated indefinitely. If an external bus arbiter is designed to wait for the M68040 to
assert BB before proceeding, then the system experiences an extended period of time in
which bus arbitration is locked. Motorola recommends that an external bus arbiter not
assume that there is a direct relationship between BR and BB or BR and BG signals.
Figure 7-32 illustrates an example of the processor requesting the bus from the external
bus arbiter. During C1, the M68040 asserts BR to request the bus from the arbiter, which
negates the alternate bus master’s BG signal and grants the bus to the processor by
asserting BG during C3. During C3, the alternate bus master completes its current access
and relinquishes the bus by three-stating all bus signals. Typically, the BB and TIP signals
MOTOROLA
040_LOCK
*
AM indicates the alternate bus master.
AM_BG
AM_BB
AM_TS
040_BG
040_BB
040_TS
040_TA
Freescale Semiconductor, Inc.
Figure 7-31. Lock Violation Example
For More Information On This Product,
INDETERMINATE
*
*
*
CONDITION
POSSIBLE
Go to: www.freescale.com
M68040 USER’S MANUAL
OWNS THE
ACTIVELY
BUS HERE
THE 040
VIOLATED
LOCK IS
7- 49