MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 404

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Once RSTI negates, the processor is internally held in reset for another 124 clocks
maximum. During the reset period, all signals that can be, are three-stated, and the rest
are driven to their inactive state. Once the internal reset signal negates, all bus signals
continue to remain in a high-impedance state until the processor is granted the bus.
Afterwards, the first bus cycle for reset exception processing begins. Figure C-2 illustrates
that the processor assumes implicit bus ownership before the first bus cycle begins.
For processor resets after the initial power-on reset, RSTI should be asserted for at least
10 clock periods. The Figure C-3 illustrates timings associated with a reset when the
processor is executing bus cycles. Note that BB and TIP (and TA if driven during a
snooped access) are negated before transitioning to a three-state level.
C-8
CDIS, MDIS*,
NOTE: * Not on MC68EC040V.
IPL2–IPL0
SIGNALS
V CC
Figure C-2. MC68040V and MC68EC040V Initial Power-On Reset Timing
BCLK
RSTI
+5 V
BUS
0 V
TIP
BG
BR
TS
BB
MI
Undefined
Freescale Semiconductor, Inc.
For More Information On This Product,
CLOCKS
t 10
>
M68040 USER’S MANUAL
Go to: www.freescale.com
CLOCKS
2
CLOCKS
128
MOTOROLA