MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 192

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

require a pullup resistor to maintain a logic-one level between bus master tenures. The
alternate bus master should negate these signals before three-stating to minimize rise
time of the signals and ensure that the processor recognizes the correct level on the next
BCLK rising edge. At the end of C3, the processor recognizes the bus grant and bus idle
conditions (BG asserted and BB negated) and assumes ownership of the bus by asserting
BB and immediately beginning a bus cycle during C4. During C6, the processor begins the
second bus cycle for the misaligned operand and negates BR since no other accesses are
pending. During C7, the external bus arbiter grants the bus back to the alternate bus
master that is waiting for the processor to relinquish the bus. The processor negates BB
and TIP before three-stating these and all other bus signals during C8. Finally, the
alternate bus master recognizes the bus grant and idle conditions at the end of C8 and is
able to resume bus activity during C9.
7-50
ATTRIBUTES
*
AM indicates the alternate bus master.
TRANSFER
AM_BG
AM_BR
D31–D0
A31–A0
BCLK
TIP
BR
BG
TA
BB
TS
*
*
C1
ALTERNATE
Figure 7-32. Processor Bus Request Timing
MASTER
Freescale Semiconductor, Inc.
For More Information On This Product,
C2
M68040 USER’S MANUAL
C3
Go to: www.freescale.com
C4
C5
PROCESSOR
C6
C7
C8
C9
ALTERNATE
MASTER
MOTOROLA