MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 20

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

1-1
1-2
1-3
1-4
3-1
3-2
4-1
4-2
4-3
4-4
5-1
5-2
5-3
5-4
5-5
5-6
5-7
6-1
6-2
7-1
7-2
7-3
7-4
7-5
7-6
8-1
8-2
8-3
8-4
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Number
Table
M68040 Data Formats ................................................................................. 1-9
Effective Addressing Modes ........................................................................ 1-10
Notational Conventions ................................................................................ 1-11
Instruction Set Summary.............................................................................. 1-14
Updating U-Bit and M-Bit for Page Descriptors............................................ 3-22
SFC and DFC Values................................................................................... 3-22
Snoop Control Encoding .............................................................................. 4-9
TLNx Encoding ............................................................................................ 4-11
Instruction-Cache Line State Transitions ..................................................... 4-15
Data-Cache Line State Transitions .............................................................. 4-17
Signal Index ................................................................................................. 5-2
Transfer-Type Encoding .............................................................................. 5-5
Normal and MOVE16 Access Transfer Modifier Encoding .......................... 5-6
Alternate Access Transfer Modifier Encoding .............................................. 5-6
Output Driver Control Groups ...................................................................... 5-11
Processor Status Encoding .......................................................................... 5-13
Signal Summary........................................................................................... 5-16
IEEE Standard 1149.1A Instructions ........................................................... 6-3
Boundary Scan Bit Definitions ..................................................................... 6-10
Data Bus Requirements for Read and Write Cycles .................................... 7-4
Summary of Access Types versus Bus Signal Encodings........................... 7-6
Memory Alignment Influence on Noncachable and
Interrupt Acknowledge Termination Summary ............................................. 7-31
TA and TEA Assertion Results ..................................................................... 7-37
M68040 Bus Arbitration States .................................................................... 7-48
Exception Vector Assignments .................................................................... 8-5
Tracing Control ............................................................................................ 8-11
Interrupt Levels and Mask Values................................................................ 8-12
Exception Priority Groups ............................................................................ 8-19
Write-Through Bus Cycles ......................................................................... 7-9
Freescale Semiconductor, Inc.
For More Information On This Product,
LIST OF TABLES
M68040 USER’S MANUAL
Go to: www.freescale.com
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