SAA7146AH NXP Semiconductors, SAA7146AH Datasheet - Page 114

• Manufacturer Part Number: SAA7146AH
• Manufacturer: NXP Semiconductors

Specifications of SAA7146AH

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
7.16.5.2
The audio input level monitoring feature allows the control of audio input levels without additional external hardware, by
comparing the absolute value of the most significant byte of an audio sample to a programmable reference maximum
level. The MAXLEVEL is defined by 7 bits, since serial audio data is transmitted in twos complement and the sign of the
compared byte is not relevant for audio level control. Therefore, MAXLEVEL is programmable from 0 to 127. The twos
complement value
32-bit level report register with one bit per time slot of TSL1 and TSL2, reporting whether there was a level violation in
that time slot. The comparison runs all the time and the level report register is reset when it is read by software.
Table 106Level report register
7.16.5.3
The WSx_CTRL bits define which of the WS lines is output and controlled by which audio interface circuit (A1 or A2).
WSx_SYNC defines the timing of WS signals.
Table 107Static function control for word select lines
Table 108Pulse width and position control
2004 Aug 25
140
00
01
10
11
00
01
10
11
WSx_SYNC
WSx_CTRL
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
OFFSET
(HEX)
[1:0]
[1:0]
Audio input level monitoring
WS line controlling
LEVEL_REPORT
3-state, input,
rising edge resets
TSL1 pointer
output, controlled
by TSL1
output, controlled
by TSL2
output,
active LOW
I
one bit clock before MSB of next time slot
WS goes active in sync with MSB and stays active until next MSB, i.e. active in sync with current time
slot
WS goes active one bit clock before MSB and stays active for one bit clock cycle, i.e. negative edge is
in sync with beginning of time slot
SINGER style: WS goes active in sync with MSB and stays active for one bit clock cycle and for two bit
clock cycles in first time slot of the superframe
2
WS0 FUNCTION
S-bus style: WS goes active one bit clock cycle before MSB of time slot and stays active until LSB, i.e.
128 is not reachable, but also not functionally needed. The comparison results are stored in the
NAME
31 to 0
3-state
output, controlled
by TSL1
output, controlled
by TSL2
output,
active LOW
WS1 FUNCTION
BIT
R
TYPE
stores the violation of MAXLEVEL for all 32 TSL records;
reset to 0000H when read.
3-state
output, controlled
by TSL1
output, controlled
by TSL2
output, active LOW output, active LOW output, active LOW
PULSE FUNCTION
WS2 FUNCTION
114
3-state
output, controlled
by TSL1
output, controlled
by TSL2
WS3 FUNCTION
DESCRIPTION
Product specification
3-state, input,
rising edge resets
TSL2 pointer
output, controlled
by TSL1
output, controlled
by TSL2
SAA7146A
WS4 FUNCTION