SAA7146AH NXP Semiconductors, SAA7146AH Datasheet - Page 54

• Manufacturer Part Number: SAA7146AH
• Manufacturer: NXP Semiconductors

Specifications of SAA7146AH

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
Table 52 Protection bits
7.8.5
Horizontal, vertical and frame synchronization signals are
either carried beside the data stream on the extra sync
pins of DD1 (one pair of sync pins per D1 channel) or are
encoded as SAV and EAV in the 8-bit wide video signal
stream. For the 16-bit wide YUV stream sync signals are
always available on separate pins. For D1 video inputs the
SAA7146A is programmed to determine where to recover
the synchronization information (from the dedicated sync
pins or from the encoded SAV and EAV codes in the data
stream).
For D1 video outputs, the SAA7146A can be programmed
to deliver synchronization information both in SAV and
EAV codes as well as on the dedicated sync pins.
Non-standard rastered video signals are supported by
sync signals at the dedicated sync pins as well as via SAV
and EAV codes. The number of clock cycles, pixels per
line and lines per field can be non-standard. These number
can range from 1 up to 4095.
The signal at the HS pin can perform the following
functions:
2004 Aug 25
7
6
5
4
3
2
1
0
NUMBER
HS: input only, the rising edge is selected to act as
timing reference
HREF: input only, gated with CREF, the rising edge is
selected as timing reference
HGT: I/O, HIGH during active video
ACT input only: HIGH during active video, inactive
during horizontal and vertical blanking
HGT and ACT: envelope all active pixels (there is no
active pixel outside HGT or ACT), but may also include
clock cycles marked as not valid pixels by means of
PXQ.
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
BIT
S
YNCHRONIZATION SIGNALS
1
0
0
0
0
0
0
0
FIXED 1
1
0
0
1
1
1
0
1
F
1
0
1
0
1
0
1
1
V
1
0
1
1
0
1
1
0
54
H
FUNCTION
The vertical sync signal can perform the following
functions:
7.8.6
The fields are detected simultaneously at both D1 sync
inputs. The results are available in two status registers.
VS: input only positive or negative, one edge is selected
as timing reference:
– If selected edge of VS and selected edge of HS are
– If selected edges of VS and HS are out of phase, then
V-DMSD: input only, falling (trailing) edge is timing
reference:
– If falling edge of V-DMSD is in high phase of HREF,
– If falling edge of V-DMSD is in low phase of HREF,
VGT: I/O, HIGH during active video, (no holes for
horizontal blanking)
FS: input only, positive or negative, frame sync,
(odd/even), (313/312, 263/262 lines) HIGH in one field,
LOW in the other, changes on full line boundaries only.
in phase, then begin 1st (odd) field
begin 2nd (even) field.
then begin 1st (odd) field
then begin 2nd (even) field.
1
1
0
0
0
1
1
1
F
P
IELD DETECTION
3
1
1
0
1
1
0
1
0
P
2
1
0
1
0
1
1
0
0
P
Product specification
1
SAA7146A
1
1
1
1
0
0
0
1
P
0