SAA7146AH NXP Semiconductors, SAA7146AH Datasheet - Page 98

• Manufacturer Part Number: SAA7146AH
• Manufacturer: NXP Semiconductors

Specifications of SAA7146AH

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
7.15.4.2
The target transfer cycle starts with applying the target
address onto the multiplexed address/data lines. By
setting the Address Strobe (AS) to LOW it is indicated that
the direction signal RWN (Read/Write Not) and the
address are valid. The AS signal is usable as a address
latch enable signal. After asserting AS LOW the
address/data lines will change to the data transfer state.
The indication of valid data in write mode or the request for
data in read mode is done by transition of Upper Data
Strobe (UDS) and/or Lower Data Strobe (LDS) to LOW.
2004 Aug 25
handbook, full pagewidth
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
AD(WR)
AD(RD)
SBHE
Target bus cycle in Motorola mode
WRN
RDN
RDY
ALE
t as
address phase
Fig.31 Intel style block transfer without address increment.
address
address
t ah
t dsw
t az
t min
98
first data phase
Since the selection of the upper and lower bytes for
transfer is done via LDS/UDS there is no need for
decoding address line AD0. Only AD15 to AD1 are
needed for transmitting the (word-)address. Slaves with
handshake ability have to drive DTACK LOW when they
have placed valid data onto AD16 in read mode or when
they have read their data in write mode. The cycle is ended
when a TIMEOUT condition at inactive DTACK or a
positive DTACK edge is detected. Then AS, LDS, UDS
and RWN are reset to HIGH. A new cycle will not start
before detection of resetting DTACK to HIGH.
write data
t dsrh
read data
t dsrd
t dhr
t rdy
t dhw
t rwi
second data phase
write data
read data
Product specification
SAA7146A
MHB064