AM7969-175JC AMD (ADVANCED MICRO DEVICES), AM7969-175JC Datasheet - Page 42

• Manufacturer Part Number: AM7969-175JC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM7969-175JC

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

38
Notes:*
10. For the TAXI Transmitter, “n” is determined by the following table:
11. t 6 (Internal Byte Boundary to CLK ) is created by the variation of internal STRB propagation delays relative to internal byte
12. X1 Pulse Width is measured at a point where CLK output equals t 2 or t 3 .
13. For the TAXI Transmitter, ‘Data’ is either DI0 – DI7, DI8/CI3, DI9/CI2, CI0 – CI1. For the TAXI Receiver, ‘STRB’ is either
14. For the TAXI Receiver, ‘n’ is determined by the state of the DMS and SERIN–
1. For conditions shown as Min or Max use the appropriate value specified under operating range.
2. The clock fall to serial output delay is typically 3 bit times.
4. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
5. If the CNB to CLK setup time is violated, IGM will stay LOW.
6. Voltage applied to either SERIN pins must not be above V CC nor below +2.5 V to assure proper operation.
7. t
8. If t 11 is not met, ACK response and timing are not guaranteed, but data will still be latched on STRB (see t 4 ).
9. Measured with device in Test mode while monitoring output logic states.
boundaries over temperatures and V CC . The internal byte boundary determines the byte in which data will come out
(SEROUT ). If STRB occurs before the byte boundary, then the data will be sent out two bytes later. If STRB occurs after the
byte boundary, then the output data will be delayed by one additional byte.
CSTRB or DSTRB and ‘Data’ is either DO0 – DO7, DO8/CO3, DO9/CO2, CO0 – CO1.
inputs. When SERIN– is held below V
4
AMD
guarantees that data is latched. ACK (t 11 ) timing may not be valid.
1
2
Open
DMS
GND
VCC
or
VCC
1
2
Open
DMS
GND
VCC
or
VCC
THT
< V
< V
< V
> 2.5 V
> 2.5 V
> 2.5 V
max or left open, n=1. When SERIN– is held above 0.25 V and when:
GND/VCC
GND/VCC
GND/VCC
THTMAX
THTMAX
THTMAX
OPEN
OPEN
OPEN
TLS
SERIN–
Am7968/Am7969
or OPEN
or OPEN
or OPEN
n = 1;
n = 10;
n = 1;
n = 11;
n = 1;
n = 12;
n = 1;
n = 10;
n = 1;
n = 1;
n = 12;
n = 11;
8 Bit
Test Mode 2
8 Bit
Local/Test Mode 1
9 Bit
Test Mode 2
9 Bit
Local/Test Mode 1
10 Bit
Test Mode 2
10 Bit
Local/Test Mode 1
“n”
8 Bit
Test Mode
8 Bit
Local Mode
9 Bit
Test Mode
9 Bit
Local Mode
10 Bit
Test Mode
10 Bit
Local Mode
“n”