AM7969-175JC AMD (ADVANCED MICRO DEVICES), AM7969-175JC Datasheet - Page 95

• Manufacturer Part Number: AM7969-175JC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM7969-175JC

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

Figure B-1
Error Detection Efficiency
When a received data pattern does not represent a valid coding symbol, the TAXI
Receiver asserts the VLTN pin to indicate that the current data contains an error.
The Receiver cannot detect the occurrence of a bit error that transforms one valid
symbol into another valid but incorrect symbol. This means that the transition error can
change a valid data symbol into a different valid data symbol, or in certain cases a valid
Command symbol and not be flagged by the Violation pin.
A single noise event on the serial link can cause at a minimum a double bit error. Single
bit errors are assumed to be impossible (or at least rare) because NRZI encoding would
require that the voltage level on the link be inverted after the event. There is no known
error mechanism external to the TAXIchip set which could cause this condition. Having
confirmed that all errors are at least 2 bits wide, let us examine the location at which
these errors can exist.
Consider the 4B/5B encoded data pattern for the TAXIchip set in the 8-bit mode. The
output corresponds to two five bit nibbles for each eight bit data byte. Shown below are
four nibbles, or two bytes of encoded data output, with six possible locations for double
bit errors within nibble 1 of Byte 2.
Notes:
Error location A corresponds to a double bit error occurring in the Least Significant Bit of nibble 2 and the
Most Significant Bit of nibble 1.
Error locations B, C, D and E occur within the nibble between adjacent bits, and,
Error location F occurs between the LSB of nibble 1 (Byte 2) and the MSB of nibble 2 (Byte 1).
APPENDIX B
MSB
b
9
b
Nibble 2
8
b
7
b
6
TAXIchip Integrated Circuit Technical Manual
LSB MSB
b
Byte 2
5
A
b
4
B
b
3
Nibble 1
C
b
2
D
b
1
E
LSB MSB
b
0
F
b
9
b
Nibble 2
8
b
7
b
6
LSB MSB
Byte 1
b
5
b
4
b
Nibble 1
3
b
2
b
1
LSB
12330E-37
b
0
91