AM7969-175JC AMD (ADVANCED MICRO DEVICES), AM7969-175JC Datasheet - Page 96

AM7969-175JC

Manufacturer Part Number
AM7969-175JC
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of AM7969-175JC

Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Package Type
PLCC
Mounting
Surface Mount
Pin Count
28
Lead Free Status / Rohs Status
Not Compliant

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Manufacturer
Quantity
Price
Part Number:
AM7969-175JC
Quantity:
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Part Number:
AM7969-175JC
Manufacturer:
AMD
Quantity:
20 000
Table B-1
Table B-2
92
AMD
For example, consider transmitting Hex B [1011], encoded as 10111. Error E occurs
changes bits b0 & b1, resulting in encoded pattern 10100, which is Hex 2 [0010]
2 bits changed, and the run length the error = 4 bits,
A double bit error can change valid data into a Violation, a valid Command byte, a 1-bit,
2-bit, 3-bit,or 4-bit data error. A summary of the occurrence of these errors for the six
error locations for 4B/5B encoding is summarized below in Table B1.
Error Type
Similar reasoning for the 5B/6B encoding scheme results in seven possible error
locations, and the summary of the occurrence of these errors is listed below:
Utilizing this information one can determine the efficiency of the violation logic in the
TAXI Receiver. Figure B2 summarizes the violation effectiveness, as well as depicting
the number of bits in error in the undetected corrupted data. This information can be
extremely useful in determining what, if any, additional error detection schemes should
be implemented. Figure B3 graphically represents the run length of the corrupted data
for the undetected errors. As shown in this figure, there are a small percentage of
unlimited run length errors. This is due to the few data patterns, which, when corrupted
will cause a false Sync pattern to be generated. This pattern will cause a running error
which will continue until the next valid Sync realigns the byte edge to its proper position.
While these false Syncs occur very rarely, these are the most dangerous errors in a
TAXI system, this very well may dictate the maximum user packet size.
1B=10
V=13
2B=6
3B=0
4B=0
C=3
1B=4
2B=2
3B=0
4B=0
A
V=5
C=5
A
2B=14
V=16
1B=0
3B=0
4B=0
C=2
1B=0
2B=8
3B=0
4B=0
1 0 1 1
0 0 1 0
B
C=3
V=5
TAXIchip Integrated Circuit Technical Manual
B
2B=12
V=12
1B=0
3B=4
4B=2
C=2
1B=2
2B=4
3B=0
4B=0
C
V=5
C=5
becomes
2 bits changed, and the run length
the error = 4 bits,
C
2B=14
1B=0
3B=6
4B=2
C=4
V=6
1B=4
2B=6
3B=0
4B=0
D
C=3
V=3
D
2B=12
1B=8
3B=0
4B=0
V=9
C=3
1B=0
2B=6
3B=0
4B=2
E
V=3
C=5
E
2B=12
V=10
1B=2
3B=0
4B=4
C=4
1B=14
2B=0
3B=0
4B=0
F
C=1
V=1
F
1B=22
2B=2
3B=0
4B=0
V=5
C=3
G

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