STV0299B STMicroelectronics, STV0299B Datasheet - Page 13

• Manufacturer Part Number: STV0299B
• Manufacturer: STMicroelectronics

Specifications of STV0299B

• Pin Count: 64
• Screening Level: Commercial
• Lead Free Status / Rohs Status: Specific Sites Compliant

4
4.3 Timing Recovery
4.3.1
The loop is parametrized by two coefficients:
alpha_tmg and beta_tmg. alpha_tmg can take
values from 0 to 4, and beta_tmg from 0 to 7
(Register 0E).
When the parameter is 0, the actual coefficient
value is zero. The 8 MSBs of the frequency
accumulator may be read or written at any time by
the I
The Symbol Frequency Registers (MSB, Middle
Bits and LSB) are in Addresses 1F, 20 and 21.
These must be programmed with the expected
symbol frequency.
The units are:
Write mode is effective when writing the Middle Bit
Register. The MSB Register must be loaded
before the Middle Bit Register.
The value of the Timing Frequency Register, when
the system is locked, is an image of the frequency
offset. The unit is f
be as close as possible to 0 (by adjusting symbol
frequency register value) in order to have a
symmetrical capture range. Reading it allows for
optimal trimming of the timing range (Register
1A).
The actual symbol frequency is:
where f
register and T
frequency register.
Table 5:
FUNCTIONAL DESCRIPTION (continued)
2
C bus—when written, all LSBs are reset.
f
s_reg
beta_tmg
S
Timing Control
act
=
1
2
3
4
5
6
7
is the content of the symbol frequency
-------------------------------------------------------------------------------------- -
f
M_CLK
mg_reg
S
/2
f
19
f
----------------
s_reg
the content of the timing
M_CLK
2
(approx. 2 ppm). It should
20
2
Natural Frequency for
+
20
2 f
f
S
alpha_tmg
s
= 20 Mbaud
0.66 kHz
0.93 kHz
1.32 kHz
1.86 kHz
2.63 kHz
3.72 kHz
5.26 kHz
T
mg_reg
4.3.2
The timing loop may be considered as a second
order loop. The natural frequency and the
damping factor may be calculated using the
following formula:
where, f
reference level and
register:
The damping factor is:
where m2 is the reference level of the AGC2
register.
Table 5 shows the natural frequency in DVB, with
nominal reference level m2 = 20, for different
values of beta_tmg and alpha_tmg, without noise.
4.3.3
The timing lock indicator reports a value
dependent upon the signal-to-noise ratio and on
the signal lock state.
With an AGC2 Reference level m2 = 20, if the
timing lock indicator is above 48, the timing is
locked; if it is above 42, this shows that a QPSK
signal is present, either locked with low C/N
(<3.6 dB) or unlocked with higher C/N; the
ambiguity may be solved by changing on purpose
the timing frequency of 1%; if it was locked before,
the indicator should be now under 42.
The indicator needs 30K symbols for stabilization
from unlock to lock after a frequency change.
The timing lock registers - the Timing Lock Setting
Register and the Timing Lock Indicator Register -
are in Addresses 11 and 17.
0.85
0.60
0.42
0.30
0.21
0.15
0.10
1
Loop Equation
S
Timing Lock Indicator
is the symbol frequency, m2 is the AGC2
f
1.70
1.20
0.85
0.60
0.42
0.30
0.21
=
n
Damping Factor
2
=
0.134
------------------------------------------------------------- -
5.2 10
=
is programmed by the timing
2
2
beta_tmg
m2 2
–
beta_tmg
6
f
3.38
2.40
1.70
1.20
0.85
0.60
0.42
S
3
m2
alpha_tmg
STV0299B
6.77
4.80
3.38
2.40
1.70
1.20
0.85
4
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