STV0299B STMicroelectronics, STV0299B Datasheet - Page 8

• Manufacturer Part Number: STV0299B
• Manufacturer: STMicroelectronics

Specifications of STV0299B

• Pin Count: 64
• Screening Level: Commercial
• Lead Free Status / Rohs Status: Specific Sites Compliant

STV0299B
4
4.1.5
For reliable operation in Normal Mode, the SCL
frequency must be lower than 1/40 of the Master
Clock (M_CLK) frequency. Consequently, care
should be taken to observe the following:
1 Before returning to Normal Mode from Standby
2 After Power-on reset signal, the STV0299B
4.1.6
The Identification Register (at address Hex 00)
gives the release number of the circuit.
The content of this register at reset is presently A1
(same as STV0299).
4.1.7
The STV0299B converts the analog inputs into
digital 6-bit I and Q flows. The sampling frequency
is f
reference described in Section 4.1.8 ‘Clock
Generation’ . The maximum value of f
MHz.
8/36
Mode, the M_CLK frequency must be selected
such that f
operates in Normal Mode. There are two possi-
ble cases:
- DIRCLK-DIS
- DIRCLK-DIS (pin 58) is tied to V
FUNCTIONAL DESCRIPTION (continued)
M_CLK = CLK_IN, the f
I
(where
frequency of the I
For example, this second operating mode is
required when the application features both a
4 MHz XTAL and a 400 kHz I
M_CLK
2
f
C bus must satisfy:
SCL
Specific Concerns about SCL
Frequency
Identification Register
Sampling Frequency
------------------ - CLK_IN
16
which is derived from an external
100
M_CLK
f
M_CLK
40
=
(pin
40 f
100
--------- - f
16
SCL
2
and f
C bus must satisfy:
CLK_IN
f
58)
SCL
SCL
SCL
), and the f
frequency of the
2
CLK_IN
-------------------- -
C bus.
is
40
DD
400 kHz.
M_CLK
grounded.
is 90
SCL
The sampling causes the repetition of the input
spectrum at each integer multiple of f
has to ensure that no frequency component is
folded in the useful signal bandwidth of f
where f
roll-off value.
4.1.8
An integrated VCO (optimised to run in the range
of 300 to 400 MHz) is locked to a reference
frequency provided by a crystal oscillator by the
following relation:
The VCO’s loop filter is optimized for a reference
frequency between 4 and 8 MHz.
The VCO generates the following by division:
• The Master Clock (M_CLK)
• An auxiliary clock (AUX_CLK) which may either
• A lower frequency, F22, typically 22 KHz,
When DIRCLK_CTRL = 1, the crystal signal is
routed directly to M_CLK; the VCO may still be
used to generate AUX_CK and/or the F22 (used
by the DiSEqC
If the internal VCO is not used by any of the
dividers, it may be stopped in order to decrease
the
emissions. The only guaranteed function in
standby mode is the I
the three clock control registers.
There are restrictions on the high and low level
durations, and on the crystal (or external clock)
frequency when the direct clock is used.
These restrictions are explained in Section 4.1.5
Specific Concerns about SCL Frequency .
be in the MHz range or in the 25 Hz to 1500 Hz
range for some specific LNB control (for
example, 60 Hz).
needed for LNB control or DiSEqC
f
power
V CO
S
Clock Generation
is the symbol frequency, and
=
f
ref
TM
consumption
4
interface).
M
+
2
C Write/Read function of
1
=
f
X TAL
and/or
4
TM
M
--------------
K
M_CLK
control.
+
+
radiation
S
1
1
(1+ )/2
is the
. One