STV0299B STMicroelectronics, STV0299B Datasheet - Page 17

• Manufacturer Part Number: STV0299B
• Manufacturer: STMicroelectronics

Specifications of STV0299B

• Pin Count: 64
• Screening Level: Commercial
• Lead Free Status / Rohs Status: Specific Sites Compliant

4
4.6.8
The serial output interface is shown in Figure 6.
The serial bit stream is available on D7,
where MSB is first to reconstruct the original
order. If RS0 = 0, then the parity bits are output
(Register 33). If RS0 = 1, the data is null during
the parity time slots.
STR_OUT is only high during the first bit of each
packet, instead of during the first byte in parallel
mode.
ERROR has the same function as in parallel
mode.
CLK_OUT is the serial bit clock; it is derived from
either the master clock, M_CLK, (if SerClk = 0 in
Registers 02 and B3), or from the internal VCO
frequency divided by 6, (if SerClk = 1), by skipping
some pulses to accommodate the frequency
difference.
Figure 6:
Figure 7:
FUNCTIONAL DESCRIPTION (continued)
CLK_OUT
D/P
STR_OUT
ERROR
Serial Output Interface
Serial Output Interface
Parallel Output Interface
RS1 = 0
RS1 = 1
STR_OUT
CLK_OUT
D/P
D7
ERROR
RS0 = 0
RS0 = 1
RS0 = 0
RS0 = 1
RS0 = 0
RS0 = 1
RS1 = 1
RS1 = 0
RS0 = 0
RS0 = 1
RS0 = 0
RS0 = 1
Data
No Error
First bit of the packet
Parity
Useful Data
Data
All of the outputs are synchronous of the same
master clock edge.
D0, STR_OUT, D/P and ERROR may be properly
sampled externally by the rising edge of
CLK_OUT, if RS1 = 0, or by the falling edge of
CLK_OUT
continuously, even during parity data, whatever
the value of RS0.
The first bit detected in a valid packet may be
decoded if it is found on the appropriate edge of
CLK_OUT, where STR_OUT = 1, ERROR = 0,
D/P = 1. The following bits only require the
assertion of D/P (while D/P = 1,...).
Outputs D0 to D6 remain at low level in serial
mode.
1/f
1 Packet
M-CLK
Uncorrectible Packet
or 6/f
VCO
if
RS1 = 1.
Parity
Parity
This
No Error
STV0299B
clock
17/36
runs