STV0299B STMicroelectronics, STV0299B Datasheet - Page 23

• Manufacturer Part Number: STV0299B
• Manufacturer: STMicroelectronics

Specifications of STV0299B

• Pin Count: 64
• Screening Level: Commercial
• Lead Free Status / Rohs Status: Specific Sites Compliant

5
TIMING LOCK SETTING REGISTER (refer to )
CARRIER FREQUENCY DETECTOR REGISTER (refer to Chapter 4.4 on page 14)
ALPHA CARRIER AND NOISE ESTIMATOR REGISTER (refer to Chapter 4.5 on page 14)
BETA CARRIER REGISTER (refer to Chapter 4.4 on page 14)
CARRIER LOCK DETECTOR THRESHOLD REGISTER (refer to Section 4.4.2 on page 14)
AGC1 INTEGRATOR REGISTER (refer to Section 4.2.2 on page 12)
TIMING LOCK INDICATOR REGISTER (refer to Section 4.3.3 on page 13)
REGISTER LIST (continued)
AGC1I
Name
TLSR
ACLC
BCLC
CLDT
TLIR
CFD
Address
HEX
11
12
13
14
15
16
17
Reset
Value
5C
R0
88
F7
88
14
Position
[7:4]
[3:0]
[6:4]
[3:2]
[1:0]
[5:4]
[3:0]
[7:6]
[5:0]
[7:0]
[7:0]
[7:0]
Bit
7
7
6
Must be programmed to 8 (to be confirmed)
Must be programmed to 4 (to be confirmed)
1: Carrier Frequency Offset Detector coupled to Carrier recover loop
0: Carrier Frequency Offset Detector disabled
Gain for Carrier Frequency Offset Detector
Time constant for Carrier Frequency Offset Detector
Lock Detector threshold to disable the Carrier Frequency Offset
Detector:
00: -16
01: -32
10: -48
11: -64
Derotator On/Off
1: On
0: Off
This bit must be programmed to zero.
Noise Estimator Time Constant
00: 4 k symbols
01: 16 k symbols
10: 64 k symbols
11: 256 k symbols
alpha_car
Bits 3, 2 and 1: b[2:0]
Bit 0: a
phase_detector_algo
Phase detector algorithm:
00: Algorithm 0 (BPSK application)
01: Algorithm 1 (QPSK application)
10: Algorithm 2 (QPSK application)
11: Reserved
beta_car
Bits 5 to 2: e[3:0]
Bit 1: c
Bit 0: d
Signed Number
AGC Integrator Value (Signed Number)
(Not Signed)
Signal Description
STV0299B
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